AD9629-40EBZ Analog Devices Inc, AD9629-40EBZ Datasheet - Page 29
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AD9629-40EBZ
Manufacturer Part Number
AD9629-40EBZ
Description
12 Bit 40 Msps Low Pwr ADC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9629BCPZRL7-20.pdf
(32 pages)
Specifications of AD9629-40EBZ
Number Of Adc's
1
Number Of Bits
12
Sampling Rate (per Second)
40M
Data Interface
Serial, SPI™
Inputs Per Adc
1 Differential
Input Range
2 Vpp
Power (typ) @ Conditions
60.5mW @ 40MSPS
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD9629
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
USR2 (Register 0x101)
Bit 3—Enable GCLK Detect
Normally set high, this bit enables a circuit that detects encode
rates below about 5 MSPS. When a low encode rate is detected,
an internal oscillator, GCLK, is enabled ensuring the proper
operation of several circuits. If set low the detector is disabled.
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Bit 2—Run GCLK
This bit enables the GCLK oscillator. For some applications
with encode rates below 10 MSPS, it may be preferable to set
this bit high to supersede the GCLK detector.
Bit 0—Disable SDIO Pull-Down
This bit can be set high to disable the internal 30 kΩ pull-down
on the SDIO pin, which can be used to limit the loading when
many devices are connected to the SPI bus.
AD9629