AD9739BBCZ Analog Devices Inc, AD9739BBCZ Datasheet - Page 45

• Manufacturer Part Number: AD9739BBCZ
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739BBCZ

• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 980mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Status bits are available in the SPI to verify that the synchron-
ization controller has found lock (Register 0x21, Bit 4), that
the synchronization controller has entered tracking mode
(Register 0x21, Bit 7), and whether the controller has lost lock
(Register 0x21, Bit 5). These bits should be polled periodically
to check the status of the controller. In addition, the user can
verify that the SYNC_IN clock is positioned correctly by
reading back the state of SYNC_SAMP1 (Register 0x0D, Bit 5)
and SYNC_SAMP0 (Register 0x0D, Bit 4). If the SYNC_IN
clock is positioned correctly, SYNC_SAMP1 should read back a
1 and SYNC_SAMP0 should read back a 0.
To ensure that all of the slaves are locked on correctly to the
master, verify the SYNC_SAMP1 and SYNC_SAMP0 bits to
ensure that the SYNC_IN_x signal has been properly placed. To
guarantee that multiple slave parts all lock correctly to one
master clock, care must be taken to ensure that the skew
between the DACCLK_x and SYNC_IN_x signals is not more
than 200 ps. If the skew is greater than this, it is possible that
not all of the slave parts will lock onto the same delay setting
from the master, and additional external delay lines may need to
be used to ensure that the SYNC_IN_x signals are positioned
correctly.
Operation in Slave Mode
When the controller is enabled in slave mode, the synchron-
ization logic simply samples the clock divider phases. The
controller uses the sampled clock divider phases to compute a
new clock divider phase rotation. This operation is shown in
Figure 95. For the slave parts to track correctly, the SYNC_OUT_x
signal must be controlled from the master and used as an input
signal into the SYNC_IN clock.
DATA RECEIVER OPERATION IN AUTO MODE
The receiver controller is enabled by setting the RCVR_CNT_
ENA bit high (Register 0x10, Bit 0). After this bit is set, the
controller enters search mode. The search mode attempts to
find the rising edge of the DCI by adjusting the delay line. The
search begins by increasing the delay line from a user-defined
starting point until the rising edge of the DCI is found. This is
followed by another search, starting from the same user-defined
point, decreasing the delay line until the other rising edge of the
DCI is found. The controller selects the closest rising edge, and
SYNC_IN_x
Figure 95. Slave Mode Tracking Mode Block Diagram
FF
FF
Rev. 0 | Page 45 of 56
0
1
CONTROLLER
the controller then enters tracking mode. The starting delay
value can be programmed via the SPI using the DCI_DEL bits
found in Register 0x13 and Register 0x14, allowing the user to
bias the closest edge selection. This value should also be
programmed into the SMP_DEL bits found in Register 0x11
and Register 0x12. To optimize the search, it is recommended to
either set the DCI_DEL bits to 0 and search up or start the
DCI_DEL bits at the midpoint and search up and down.
Tracking mode uses two sampling clocks to traverse the rising
edge of DCI. The pre sample clock should always sample DCI
low. The post sample clock should always sample DCI high. The
controller uses the samples from the pre and post registers to
adjust the delay lines and maintain lock with the user DCI, as
shown in Figure 96. The skew between the pre- and post-sample
clocks is user adjustable via the FINE_DEL_SKW[3:0] bits
(Register 0x13, Bits[3:0]). The value of the FINE_DEL_SKEW
bits determines how closely the controller tracks the rising edge
of DCI and, indirectly, the speed of the loop. Each step of the
FINE_DEL_SKW bits is 20 ps, allowing for a total skew of 300 ps.
Each of the delay lines has a 1 ns range for a total adjustment
range of ±2 ns.
The tracking controller operates continuously in the background.
Monitoring the status of DCI_PRE_PH0 (Register 0x0C, Bit 2)
and DCI_PST_PH0 (Register 0x0C, Bit 0) allows the user to
verify whether the sampling of the DCI is occurring correctly. If
the delay settings are correct, the state of DCI_ PRE_PH0
should be 0 and the state of DCI_PST_PH0 should be 1.
The search and tracking modes use Clock Phase 0 to lock onto
the DCI. When the controller is locked, Clock Phase 1 is placed
in the center of the data sampling period. Figure 97 shows the
clock and DCI phase relationships.
The data receiver controller can be set up to loop when an error
occurs by setting the RCVR_LOOP_ON bit in the SPI (Register
0x10, Bit 1). If this bit is set, the controller generates an IRQ and
restart, beginning with the clock phase determination, followed
FINE_DEL_PRE
FINE_DEL_PST
0
2
1
3
Figure 96. Pre- and Post-Delay Sampling Diagram
DCI
0
2
1
3
PHASE
/4
FINE_DEL
SKW
DAC
CLOCK
AD9739