AD9739BBCZ Analog Devices Inc, AD9739BBCZ Datasheet - Page 50

• Manufacturer Part Number: AD9739BBCZ
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739BBCZ

• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 980mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9739
RECOMMENDED START-UP SEQUENCE
The steps necessary to optimize the performance of the part and generate an output waveform are as follows:
1.
Table 35.
Register
CNT_CLK
_Dis
FSC_1
FSC_2
1
2.
Table 36. Normal Mode
Register
Decoder_
CNT
1
Table 37. RZ Mode
Register
Decoder_
CNT
1
Table 38. Mix Mode
Register
Decoder_
CNT
1
3.
Table 39.
Register
CROS_CNT1
CROS_CNT2
1
4.
The two-digit number is the decimal representation of the address.
The two-digit number is the decimal representation of the address.
The two-digit number is the decimal representation of the address.
The two-digit number is the decimal representation of the address.
The two-digit number is the decimal representation of the address.
Enable clocks to the controller and set the full-scale current. The registers and bits used in this step are shown in Table 35.
Recommended values for the bits are in parentheses.
Select the decoder mode. Recommended values for the bits are in parenthesis in Table 36, Table 37, and Table 38.
Set the cross control to the optimal setting. Recommended values for the bits are in parenthesis in Table 39.
Enable the mu controller and ensure that it locks. Recommended values for the bits are in parenthesis in Table 40. To optimize and
lock the mu controller, it is only necessary to have the DAC clock running; no data need be presented to the DAC to optimize this
controller. It is recommended to write to Register 0x26 last, after all other mu controller registers in the table are written to, to ensure
that the controller is set up correctly before it is enabled.
Address
0x02
0x06
0x07
Address
0x08
Address
0x08
Address
0x08
Address
0x22
0x23
02
06
07
08
08
08
1
1
1
1
34
35
1
Bit 7
N/A
FSC[7] (0)
Sleep (0)
Bit 7
N/A
Bit 7
N/A
Bit 7
N/A
Bit 7
N/A
N/A
Bit 6
N/A
Bit 6
N/A
Bit 6
N/A
Bit 6
N/A
N/A
Bit 6
N/A
FSC[6]
(0)
N/A
Bit 5
N/A
Bit 5
N/A
Bit 5
N/A
Bit 5
N/A
N/A
Bit 5
N/A
FSC[5]
(0)
N/A
Bit 4
N/A
Bit 4
Bit 4
N/A
N/A
Bit 4
DIR_P (0)
DIR_N (0)
Bit 4
N/A
FSC[4]
(0)
N/A
Rev. 0 | Page 50 of 56
Bit 3
N/A
Bit 3
N/A
Bit 3
N/A
Bit 3
CLKP_OFFSET
[3] (1)
CLKN_OFFSET
[3] (1)
Bit 3
CLKGEN_PD
(0)
FSC[3] (0)
N/A
Bit 2
N/A
Bit 2
N/A
Bit 2
N/A
Bit 1
DAC_DEC[1] (1)
Bit 1
DAC_DEC[1] (0)
Bit 1
DAC_DEC[1] (0)
Bit 2
N/A
FSC[2]
(0)
N/A
Bit 2
CLKP_
OFFSET
[2] (1)
CLKN_
OFFSET
[2] (1)
Bit 1
REC_CNT_
CLK (1)
FSC[1] (0)
FSC[9] (1)
Bit 1
CLKP_
OFFSET[1]
(1)
CLKN_
OFFSET[1]
(1)
Bit 0
DAC_DEC[0] (0)
Bit 0
DAC_DEC[0] (0)
Bit 0
DAC_DEC[0] (1)
Bit 0
MU_CNT_
CLK (1)
FSC[0] (0)
FSC[8] (0)
Bit 0
CLKP_
OFFSET[
0] (1)
CLKN_
OFFSET
[0] (1)
Recommended
Value
0x03
0x00
0x02
Recommended
Value
0x00
Recommended
Value
0x01
Recommended
Value
0x02
Recommended
Value
0x0F
0x0F