AD9765-EBZ Analog Devices Inc, AD9765-EBZ Datasheet - Page 2

• Manufacturer Part Number: AD9765-EBZ
• Description: 12-Bit, 125 MSPS DUal TxDAC+
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9765-EBZ

• Number Of Dac's: 2
• Number Of Bits: 12
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 125M
• Data Interface: Parallel
• Settling Time: 35ns
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9765
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AN-555
Analog and digital supplies can be run at either 3 V or
5 V, and do not have to run from the same supply volt-
age. Regardless of supply voltage, the digital input data
can be safely run from 3 V or 5 V logic levels, as long as
the proper resistor packs are placed in the digital input
data path (see Digital Inputs section).
DIGITAL INPUTS
The digital inputs on the dual DAC evaluation board are
designed to accept inputs from any generic word gen-
erator. However, when running the DAC at high sample
rates, the quality of the digital data can have an impact
on the performance of the DAC. As an example, if the
edges of the digital information are slow, or the edges of
the various bits are skewed from each other in time,
specifications such as SNR and SINAD may be degraded.
The digital input path on the evaluation board includes
both pull-up and pull-down plug-in resistor packs. The
pull down resistors allow the user to apply digital logic
at 5 V levels when the DAC digital supply is operating at
3 V, and the pull-ups allow 3 V logic levels when the DAC
is run from a 5 V digital supply. The digital input signal
path is shown in Figure 3.
Figure 3. Input Structure of Digital Input Signal Path on
Dual DAC Evaluation Board
EVALUATION BOARD
NOT SUPPLIED WITH
DIGITAL DATA
INPUT
WRT1IN
WRT2IN
CLK1IN
CLK2IN
IQWRT
RESET
IQCLK
IQSEL
Figure 4. Jumper Options for Clock Input Section on Dual DAC Evaluation Board
S1
S2
S3
S4
DGND
22
DVDD
TP32
TP30
TP31
TP29
NOT SUPPLIED WITH
EVALUATION BOARD
NOT SUPPLIED WITH
EVALUATION BOARD
DATA INPUT ON
AD9763/AD9765/AD9767
R1
50
R2
50
R3
50
DCLKIN1
R4
50
JP16
JP5
JP4
JP3
I
I
I
–2–
C
C
C
JP9
CLOCK INPUTS
SMA connectors S1 to S4 are intended to be used as
clock and control lines for the AD976x, and are 50
minated. The selection of JP9 also allows the user to
select a clock generated on the same digital data bus as
the input data.
Jumpers JP1 to JP7, JP9, and JP16 control the clock
inputs for the various clock modes in which the dual
DACs can operate. It is recommended that the clock
source be a square wave with minimal overshoot and
undershoot. Overshoot and undershoot beyond the sup-
ply rails can inject noise onto the clock, which may result
in jitter and reduced DAC performance. The dual DACs
can operate with a sine wave clock, but dynamic perfor-
mance will be degraded. Figure 4 shows the clock input
section and jumper options for the dual DAC evaluation
board.
MODES OF OPERATION
The AD976x dual DAC family is designed to operate
either as two completely separate DACs in dual DAC
mode, or with a single digital input port in which the input
data is alternately sent to either of the two DACs (inter-
leaving mode).
DCLKIN2
DVDD
JP2
JP1
DVDD
DVDD
AD9709/AD9763/AD9765/AD9767
WRT1/IQWRT
CLK1/IQCLK
CLK2/IQRESET
WRT2/IQSEL
K
J
D
CLK
CLR
H
PRE
H L
JP6
U1
1
L
JP7
Q
74HC112
DGND;8
DVDD;16
REV. 0
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