AD9773BSVRL Analog Devices Inc, AD9773BSVRL Datasheet
AD9773BSVRL
Specifications of AD9773BSVRL
Related parts for AD9773BSVRL
AD9773BSVRL Summary of contents
Page 1
FEATURES 12-bit resolution, 160 MSPS/400 MSPS input/output data rate Selectable 2×/4×/8× interpolating filter Programmable channel gain and offset adjustment f / digital quadrature modulation capability Direct IF transmission mode for 70 MHz + ...
Page 2
AD9773 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .......................................................... 1 Table of Contents .............................................................................. 2 Revision History ........................................................................... 2 General Description ......................................................................... 4 Product Highlights ....................................................................... 4 Specifications..................................................................................... 5 DC Specifications ......................................................................... 5 Dynamic Specifications ............................................................... ...
Page 3
B to Rev. C Updated Formatting .........................................................Universal Changes to Figure 32 .................................................................... 22 Changes to Figure 108 .................................................................. 55 Updated Outline Dimensions ..................................................... 58 Changes to Ordering Guide......................................................... 58 4/04—Data Sheet Changed from Rev Rev. B. Update ...
Page 4
AD9773 GENERAL DESCRIPTION 1 The AD9773 is the 12-bit member of the AD977x pin- compatible, high performance, programmable 2×/4×/8× interpolating TxDAC+® family. The AD977x family features a serial port interface (SPI) that provides a high level of programmability, thus allowing ...
Page 5
SPECIFICATIONS DC SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3 MIN MAX Table 1. Parameter RESOLUTION 1 DC Accuracy Integral Nonlinearity Differential Nonlinearity Monotonicity ANALOG OUTPUT ...
Page 6
AD9773 DYNAMIC SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = MIN MAX transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE ...
Page 7
DIGITAL SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3 MIN MAX Table 3. Parameter DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic ...
Page 8
AD9773 DIGITAL FILTER SPECIFICATIONS Table 4. Half-Band Filter No. 1 (43 Coefficients) Tap Coefficient − −134 ...
Page 9
ABSOLUTE MAXIMUM RATINGS Table 7. Parameter AVDD, DVDD, CLKVDD AVDD, DVDD, CLKVDD AGND, DGND, CLKGND REFIO, FSADJ1/FSADJ2 OUTA OUTB P1B11 to P1B0, P2B11 to P2B0, RESET DATACLK, PLL_LOCK CLK+, CLK− LPF SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO Junction Temperature ...
Page 10
AD9773 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLKVDD LPF CLKVDD CLKGND CLK+ CLK– CLKGND DATACLK/PLL_LOCK DGND DVDD P1B11 (MSB) P1B10 P1B9 P1B8 P1B7 P1B6 DGND DVDD P1B5 P1B4 CONNECT ...
Page 11
Table 8. Pin Function Descriptions Pin No. Mnemonic 1, 3 CLKVDD 2 LPF 4, 7 CLKGND 5 CLK+ 6 CLK− 8 DATACLK/PLL_LOCK 9, 17, 25, DGND 35, 44, 52 10, 18, 26, DVDD 36, 43 16, P1B11 ...
Page 12
AD9773 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3 Ω doubly terminated, unless otherwise noted –10 –20 –30 –40 –50 –60 –70 –80 – ...
Page 13
FREQUENCY (MHz) Figure 12. Single-Tone Spectrum @ f = 160 MSPS with f DATA 90 85 0dBFS –12dBFS –6dBFS ...
Page 14
AD9773 90 8× 85 4× 1× 70 2× FREQUENCY (MHz) Figure 18. Third-Order IMD Products vs. f OUT 1× 160 MSPS, 2× 160 MSPS, 4× f DATA ...
Page 15
FREQUENCY (MHz) Figure 24. Single-Tone Spurious Performance 150 MSPS, No Interpolation DATA 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 ...
Page 16
AD9773 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 100 200 FREQUENCY (MHz) Figure 30. Single-Tone Spurious Performance MSPS, Interpolation = 8× DATA 0 –10 –20 –30 –40 –50 –60 –70 –80 ...
Page 17
TERMINOLOGY Adjacent Channel Power Ratio (ACPR) A ratio, in dBc, between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These ...
Page 18
AD9773 MODE CONTROL (VIA SPI PORT) 1 Table 9. Mode Control via SPI Port Address Bit 7 Bit 6 00h SDIO LSB, MSB First Bidirectional 0 = MSB 0 = Input 1 = LSB 1 = I/O 01h Filter Filter ...
Page 19
Address Bit 7 Bit 6 0Ah 0Bh QDAC QDAC Offset Offset Adjustment Adjustment Bit 9 Bit 8 0Ch QDAC I OFFSET Direction OFFSET on I OUTA OFFSET on I OUTB 0Dh 1 Default values ...
Page 20
AD9773 REGISTER DESCRIPTION Address 00h Bit 7: Logic 0 (default) causes the SPI_SDIO pin to act as an input during the data transfer (Phase 2) of the communications cycle. When set to 1, SPI_SDIO can act as an input or ...
Page 21
Address 03h Bit 7: Allows the data rate clock (divided down from the DAC clock output at either the DATACLK pin (Pin the SPI_SDO pin (Pin 53). The default this bit enables ...
Page 22
AD9773 FUNCTIONAL DESCRIPTION The AD9773 dual interpolating DAC consists of two data channels that can be operated completely independently or coupled to form a complex modulator in an image reject transmit architecture. Each channel includes three FIR filters, making the ...
Page 23
INSTRUCTION BYTE The instruction byte contains the information shown in Table 15. Table 15 Description 0 0 Transfer 1 Byte 0 1 Transfer 2 Bytes 1 0 Transfer 3 Bytes 1 1 Transfer 4 Bytes R/W Bit 7 ...
Page 24
AD9773 INSTRUCTION CYCLE CS SCLK SDIO R (N) (N) SDO INSTRUCTION CYCLE CS SCLK SDIO SDO CS SCLK SDIO CS SCLK SDIO SDO ...
Page 25
... In the Interfacing the AD9773 with the AD8345 Quadrature Modulator section, the performance data shows to what degree image rejection can be improved when the AD9773 is used with an AD8345 quadrature modulator from Analog Devices Inc. CONTROL REGISTERS REFIO frequency is stable after Rev ...
Page 26
AD9773 0 –0.5 1R MODE –1.0 2R MODE –1.5 –2.0 –2.5 –3.0 0 200 400 600 FINE GAIN REGISTER CODE 2 = 1.9k Ω ) (ASSUMING SET SET Figure 40. Fine Gain Effect on I The offset ...
Page 27
CLOCK INPUT CONFIGURATIONS The clock inputs to the AD9773 can be driven differentially or single-ended. The internal clock circuitry has supply and ground (CLKVDD, CLKGND) separate from the other supplies on the chip to minimize jitter from internal noise sources. ...
Page 28
AD9773 CLK+ CLK– PLL_LOCK 1 = LOCK LOCK INTERPOLATION PHASE FILTERS, DETECTOR MODULATORS, AND DACS CLOCK PRESCALER INPUT DISTRIBUTION DATA CIRCUITRY LATCHES INTERNAL SPI CONTROL REGISTERS INTERPOLATION RATE MODULATION CONTROL RATE SPI PORT ...
Page 29
Figure 48. PLL_LOCK Output Signal (Pin 8) in the Process of Locking (Typical Lock Time important to note that the resistor/capacitor needed for the PLL loop filter is internal on the AD9773. This suffices unless the input data ...
Page 30
AD9773 TWO-PORT DATA INPUT MODE The digital data input ports can be configured as two independent ports single (one-port mode) port. In the two-port mode, data at the two input ports is latched into the AD9773 on ...
Page 31
DATACLK INVERSION (Control Register 02h, Bit 4) By programming this bit, the DATACLK signal shown in Figure 52 can be inverted. With inversion enabled, t the time between the rising edge of CLKIN and the falling edge of DATACLK. No ...
Page 32
AD9773 ONEPORTCLK DRIVER STRENGTH The drive capability of ONEPORTCLK is identical to that of DATACLK in the two-port mode. Refer to Figure 53 for performance under load conditions CLKIN ONEPORTCLK I AND Q INTERLEAVED INPUT DATA AT PORT ...
Page 33
Under these conditions, IQSEL = 0 latches the data into the I channel on the clock rising edge, while IQSEL = 1 latches the data into the Q channel possible to invert the I and Q selection by ...
Page 34
AD9773 MODULATION, NO INTERPOLATION With Control Register 01h, Bit 7 and Bit 6 set to 00, the interpolation function on the AD9773 is disabled. Figure 59 to Figure 62 show the DAC output spectral characteristics of the AD9773 in the ...
Page 35
MODULATION, INTERPOLATION = 2× With Control Register 01h, Bit 7 and Bit 6 set to 01, the inter- polation rate of the AD9773 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence ...
Page 36
AD9773 MODULATION, INTERPOLATION = 4× With Control Register 01h, Bit 7 and Bit 6 set to 10, the inter- polation rate of the AD9773 is 4×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the ...
Page 37
MODULATION, INTERPOLATION = 8× With Control Register 01h, Bit 7 and Bit 6 set to 11, the interpolation rate of the AD9773 is 8×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, ...
Page 38
AD9773 ZERO STUFFING (Control Register 01h, Bit 3) As shown in Figure 75 null in the output frequency response of the DAC (after interpolation, modulation, and DAC reconstruction) occurs at the final DAC sample rate (f is ...
Page 39
INPUT (REAL) OUTPUT (REAL) INPUT (IMAGINARY) 90° OUTPUT (IMAGINARY) –jω COSωt + jSINωt Figure 77. Implementation of a Complex Modulator COMPLEX MODULATION AND IMAGE REJECTION OF BASEBAND SIGNALS In traditional transmit applications, a two-step upconversion is done in ...
Page 40
AD9773 REAL CHANNEL (IN IMAGINARY CHANNEL (IN REAL QUADRATURE MODULATOR IMAGINARY COMPLEX MODULATION FREQUENCY QUADRATURE MODULATION FREQUENCY Q REAL CHANNEL (OUT) A – C –B/2J f – ...
Page 41
COMPLEX BASEBAND SIGNAL 1 e j(ω1 + ω2)t × OUTPUT = REAL 1/2 = REAL –ω1 – ω2 DC Figure 80. Two-Stage Complex Upconversion IMAGE REJECTION AND SIDEBAND SUPPRESSION OF MODULATED CARRIERS As shown in Figure 79, image rejection can ...
Page 42
AD9773 The complex carrier synthesized in the AD9773 digital modu- lator is accomplished by creating two real digital carriers in quadrature. Carriers in quadrature cannot be created with the modulator running result, complex modulation DAC ...
Page 43
–40 –60 –80 –100 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 (LO (× ) OUT DATA Figure 83. 2x Interpolation, Complex f DAC 0 – ...
Page 44
AD9773 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 FREQUENCY (MHz) Figure 89. AD9773 Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 4x, No Modulation in AD9773 0 ...
Page 45
FREQUENCY (MHz) Figure 93. AD9773 Real DAC Output of Complex Input Signal Near Baseband (Negative Frequencies Only), Interpolation = 4x, Complex Modulation in AD9773 = −f ...
Page 46
AD9773 APPLYING THE OUTPUT CONFIGURATIONS The following sections illustrate typical output configurations for the AD9773. Unless otherwise noted assumed that I is set to a nominal 20 mA. For applications requiring OUTFS optimum dynamic performance, a differential output ...
Page 47
DIFFERENTIAL COUPLING USING AN OP AMP An op amp can also be used to perform a differential-to-single- ended conversion, as shown in Figure 99. This has the added benefit of providing signal gain as well. In Figure 99, the AD9773 ...
Page 48
AD9773 EVALUATION BOARD The AD9773 evaluation board allows easy configuration of the various modes, programmable via the SPI port. Software is available for programming the SPI port from Windows 95®, Windows 98®, or Windows NT®/2000. The evaluation board also contains ...
Page 49
INPUT CLOCK AWG2021 OR DG2020 JUMPER CONFIGURATION FOR TWO-PORT MODE, PLL ON SOLDERED/IN JP1 – JP2 – JP3 – JP5 – JP6 – JP12 – JP24 – JP25 – JP26 – JP27 – JP31 – JP32 – JP33 – NOTES ...
Page 50
AD9773 NOTES 1. TO USE PECL DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1 TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT ...
Page 51
RC0603 G2 ENBL G3 VPS1 VOUT LOIP VPS2 LOIN G4A G1B G4B G1A QBBN IBBN QBBP IBBP ADTL1-12 CC0603 Figure 105. AD8345 Circuitry on AD9773 Evaluation Board Rev Page RC0603 ADTL1-12 CC0805 AD9773 ...
Page 52
AD9773 CC0603 RC0603 CC0603 RC1206 CC0603 RC0603 CC0605 Figure 106. AD9773 Clock, Power Supplies, and Output Circuitry Rev Page CC0805 ...
Page 53
Figure 107. AD9773 Evaluation Board Input (A Channel) and Clock Buffer Circuitry Rev Page AD9773 ...
Page 54
AD9773 Figure 108. AD9773 Evaluation Board Input (B Channel) and SPI Port Circuitry Rev Page ...
Page 55
Figure 109. AD9773 Evaluation Board Components, Top Side Figure 110. AD9773 Evaluation Board Components, Bottom Side Rev Page AD9773 ...
Page 56
AD9773 Figure 112. AD9773 Evaluation Board Layout, Layer Two (Ground Plane) Figure 111. AD9773 Evaluation Board Layout, Layer One (Top) Rev Page ...
Page 57
Figure 113. AD9773 Evaluation Board Layout, Layer Three (Power Plane) Figure 114. AD9773 Evaluation Board Layout, Layer Four (Bottom) Rev Page AD9773 ...
Page 58
... SEATING 0.05 0.08 MAX PLANE COPLANARITY VIEW A ROTATED 90 ° CCW ORDERING GUIDE Model Temperature Range AD9773BSV −40°C to +85°C AD9773BSVRL −40°C to +85°C AD9773BSVZ 1 −40°C to +85°C 1 AD9773BSVZRL −40°C to +85°C AD9773- RoHS Compliant Part. 14.20 14. ...
Page 59
NOTES Rev Page AD9773 ...
Page 60
AD9773 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02857-0-10/07(D) Rev Page ...