AD9773BSVRL Analog Devices Inc, AD9773BSVRL Datasheet - Page 3

• Manufacturer Part Number: AD9773BSVRL
• Description: IC,D/A CONVERTER,DUAL,12-BIT,CMOS,TQFP,80PIN
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9773BSVRL

• Rohs Status: RoHS non-compliant
• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 410mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• For Use With: AD9773-EBZ - BOARD EVALUATION AD9773

1/06—Rev. B to Rev. C
Updated Formatting .........................................................Universal
Changes to Figure 32 .................................................................... 22
Changes to Figure 108 .................................................................. 55
Updated Outline Dimensions ..................................................... 58
Changes to Ordering Guide......................................................... 58
4/04—Data Sheet Changed from Rev. A to Rev. B.
Update Layout....................................................................Universal
Changes to DC Specifications ....................................................... 5
Changes to Absolute Maximum Ratings...................................... 9
Changes to DAC Operation Section........................................... 25
Inserted Figure 38.......................................................................... 25
Changes to Figure 40 .................................................................... 26
Changes to Table 11 ...................................................................... 28
Changes to Programmable PLL Section..................................... 29
Changes to Power Dissipation Section....................................... 29
Changes to Figures 49, 50, and 51............................................... 29
Changes to PLL Enabled, One-Port Mode Section .................. 31
Changes to PLL Disabled, One-Port Mode Section ................. 32
Changes to Figure 102 .................................................................. 49
Changes to Figure 104 .................................................................. 50
Updated Ordering Guide ............................................................. 58
Updated Outline Dimensions...................................................... 58
Rev. D | Page 3 of 60
3/03—Data Sheet Changed from Rev. 0 to Rev. A.
Edits to Features ...............................................................................1
Edits to DC Specifications ..............................................................3
Edits to Dynamic Specifications ....................................................4
Edits to Pin Function Descriptions ...............................................7
Edits to Table I ............................................................................... 14
Edits to Register Description—Address 02h Section............... 15
Edits to Register Description—Address 03h Section............... 16
Edits to Register Description—Address 07h, 0Bh Section...... 16
Edits to Equation 1........................................................................ 16
Edits to MSB/LSB Transfers Section........................................... 18
Changes to Figure 8 ...................................................................... 20
Edits to Programmable PLL Section........................................... 21
Added New Figure 14 ................................................................... 22
Renumbered Figures 15 through 69 ........................................... 22
Add Two-Port Data Input Mode Section................................... 23
Edits to PLL Enabled, Two-Port Mode Section ........................ 24
Edits to Figure 19 .......................................................................... 24
Edits to Figure 21 .......................................................................... 25
Edits to PLL Disabled, Two-Port Mode Section ....................... 25
Edits to Figure 22 .......................................................................... 25
Edits to Figure 23 .......................................................................... 26
Edits to Figure 26a ........................................................................ 27
Edits to Complex Modulation and Image Rejection of
Baseband Signals Section ............................................................. 31
Changes to Figures 53 and 54...................................................... 38
Edits to Evaluation Board Section .............................................. 39
Changes to Figures 56 through 59 .............................................. 40
Replaced Figures 60 through 69.................................................. 42
Updated Outline Dimensions...................................................... 49
AD9773