AD977AARZ Analog Devices Inc, AD977AARZ Datasheet - Page 4

• Manufacturer Part Number: AD977AARZ
• Description: 200 KSPS 16 BIT ADC
• Manufacturer: Analog Devices Inc

Specifications of AD977AARZ

• Number Of Bits: 16
• Sampling Rate (per Second): 200k
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 100mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Number Of Elements: 1
• Resolution: 16Bit
• Architecture: SAR
• Sample Rate: 200KSPS
• Input Polarity: Unipolar/Bipolar
• Input Type: Voltage
• Differential Input: No
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 100mW
• Differential Linearity Error: ±3LSB
• Integral Nonlinearity Error: ±3LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: SOIC W
• Input Signal Type: Single-Ended
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD977/AD977A–SPECIFICATIONS
Parameter
DIGITAL INPUTS
DIGITAL OUTPUTS
POWER SUPPLIES
TEMPERATURE RANGE
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Convert Pulsewidth
R/C, CS to BUSY Delay
BUSY LOW Time
BUSY Delay after End of Conversion
Aperture Delay
Conversion Time
Acquisition Time
Throughput Time
R/C Low to DATACLK Delay
DATACLK Period
DATA Valid Setup Time
DATA Valid Hold Time
EXT. DATACLK Period
EXT. DATACLK HIGH
EXT. DATACLK LOW
R/C, CS to EXT. DATACLK Setup Time
R/C to CS Setup Time
EXT. DATACLK to SYNC Delay
EXT. DATACLK to DATA Valid Delay
CS to EXT. DATACLK Rising Edge Delay
Previous DATA Valid after CS, R/C Low
BUSY to EXT. DATACLK Setup Time
Final EXT. DATACLK to BUSY Rising Edge
TAG Valid Setup Time
TAG Valid Hold Time
Specifications subject to change without notice.
Logic Levels
Data Format
Data Coding
Pipeline Delay
Specified Performance
Power Dissipation
Specified Performance
V
V
I
I
V
V
V
V
I
I
PWRD LOW
PWRD HIGH
IL
IH
DIG
ANA
IL
IH
OL
OH
DIG
ANA
Conditions
I
I
T
SINK
SOURCE
(AD977A: F
MIN
= 1.6 mA
to T
= 500 µA
MAX
S
= 200 kHz, AD977: F
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
+ t
Min
–0.3
2.0
Conversion Results Only Available after Completed Conversion
4
4.75
4.75
–40
7
(Both Specs)
S
Binary Two’s Complement or Straight Binary
= 100 kHz, V
Min
50
1.0
50
20
66
20
30
20
10
15
25
10
3.5
5
0
20
A, B, C Grades
AD977A
Typ
50
40
3.8
220
220
DIG
Typ
Serial 16-Bits
5
5
4
11
50
= V
ANA
Max
83
4.0
4.0
5
t
66
66
1.7
12
= 5 V, –40 C to +85 C)
+ 5
Min
50
2.0
100
20
100
20
30
20
10
15
25
10
7.5
5
0
20
AD977
Typ
50
40
7.6
350
450
Max
+0.8
V
± 10
± 10
0.4
5.25
5.25
100
+85
DIG
Max
83
8.0
8.0
10
t
66
66
3.5
+ 0.3
12
+ 5
Unit
V
V
µA
µA
V
V
V
V
mA
mA
mW
µW
°C
Unit
ns
ns
µs
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
ns
ns