AD9861-50EBZ Analog Devices Inc, AD9861-50EBZ Datasheet - Page 30

• Manufacturer Part Number: AD9861-50EBZ
• Description: 10 Bit, 50 MSPS MxFE Converter
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9861-50EBZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: AD9861-50
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9861
DIGITAL BLOCK
The AD9861 digital block allows the device to be configured in
various timing and operation modes. The following sections
discuss the flexible I/O interfaces, the clock distribution block,
and the programming of the device through mode pins or SPI
registers.
Table 11. Flexible Data Interface Modes
Mode
Name
HD20
HD10
FD
Clone
Tx Only Mode (Half-Duplex)
AD9861
AD9861
AD9861
AD9861
IFACE1
IFACE2
IFACE3
IFACE1
IFACE2
IFACE3
IFACE1
IFACE2
IFACE3
IFACE1
IFACE2
IFACE3
U[0:9]
U[0:9]
U[0:9]
U[0:9]
L[0:9]
L[0:9]
L[9]
L[9]
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
Tx_A/B DATA
Tx_A/B DATA
Tx_A/B DATA
Tx_A DATA
Tx_B DATA
TxSYNC
TxSYNC
TxSYNC
Tx/Rx
Tx/Rx
Tx/Rx
03606-0-008
03606-0-009
03606-0-010
03606-0-011
DIGITAL
DIGITAL
DIGITAL
DIGITAL
BACK
BACK
BACK
BACK
END
END
END
END
Rx Only Mode (Half-Duplex)
AD9861
AD9861
AD9861
AD9861
IFACE1
IFACE2
IFACE3
IFACE1
IFACE2
IFACE3
IFACE1
IFACE2
IFACE3
IFACE1
IFACE2
IFACE3
U[0:9]
U[0:9]
U[0:9]
L[0:9]
L[0:9]
L[0:9]
L[0:9]
U[9]
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
Rx_A/B DATA
Rx_A/B DATA
Rx_A DATA
Rx_B DATA
Rx_A DATA
Rx_B DATA
RxSYNC
Tx/Rx
Tx/Rx
Tx/Rx
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03606-0-012
03606-0-013
03606-0-014
03606-0-015
DIGITAL
DIGITAL
DIGITAL
DIGITAL
BACK
BACK
BACK
BACK
END
END
END
END
Flexible I/O Interface Options
The AD9861 can accommodate various data interface transfer
options (flexible I/O). The AD9861 uses two 10-bit buses, an
upper bus (U10) and a lower bus (L10), to transfer the dual-
channel 10-bit ADC data and dual-channel 10-bit DAC data by
means of interleaved data, parallel data, or a mix of both. Table 11
shows the different I/O configurations of the modes depending
on half-duplex or full-duplex operation. Table 12 and Table 13
summarize the pin configurations versus the modes.
Concurrent Tx + Rx Mode
(Full-Duplex)
AD9861
IFACE1
IFACE2
IFACE3
U[0:9]
L[0:9]
OUTPUT CLOCK
OUTPUT CLOCK
Rx_A/B DATA
Tx_A/B DATA
TxSYNC
N/A
N/A
N/A
03606-0-016
DIGITAL
BACK
END
General Notes
Rx Data Rate
Two 10-Bit Parallel Rx Data
Tx Data Rate
Two 10-Bit Parallel Tx Data
Rx Data Rate
One 10-Bit Interleaved Rx
Tx Data Rate
One 10-Bit Interleaved Tx
Rx Data Rate
One 10-Bit Interleaved Rx
Tx Data Rate
One 10-Bit Interleaved Tx
Rx Data Rate
Two 10-Bit Parallel Rx Data
Tx Data Rate
One 10-Bit Interleaved Tx
Requires SPI Interface to
Configure; Similar to AD9860
Data Interface
Buses
Buses
Data Bus
Data Bus
Data Bus
Data Bus
Buses
Data Bus
= 1 × ADC Sample Rate
= 1 × ADC Sample Rate
= 2 × ADC Sample Rate
= 2 × ADC Sample Rate
= 2 × ADC Sample Rate
= 2 × ADC Sample Rate
= 1 × ADC Sample Rate
= 2 × ADC Sample Rate