AD9985BSTZ-110 Analog Devices Inc, AD9985BSTZ-110 Datasheet

IC,Data Acquisition Signal Conditioner,3-CHANNEL,8-BIT,CMOS,QFP,80PIN,PLASTIC

AD9985BSTZ-110

Manufacturer Part Number
AD9985BSTZ-110
Description
IC,Data Acquisition Signal Conditioner,3-CHANNEL,8-BIT,CMOS,QFP,80PIN,PLASTIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9985BSTZ-110

Applications
Video
Interface
Serial Port
Voltage - Supply
2.2 V ~ 3.45 V
Package / Case
80-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9985BSTZ-110
Manufacturer:
Analog Devices Inc
Quantity:
10 000
FEATURES
Automated clamping level adjustment
140 MSPS maximum conversion rate
300 MHz analog bandwidth
0.5 V to 1.0 V analog input range
500 ps p-p PLL clock jitter at 110 MSPS
3.3 V power supply
Full sync processing
Sync detect for hot plugging
Midscale clamping
Power-down mode
Low power: 500 mW typical
4:2:2 output format mode
APPLICATIONS
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TV
GENERAL DESCRIPTION
The AD9985 is a complete 8-bit, 140 MSPS, monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode rate
capability and full power analog bandwidth of 300 MHz
support resolutions up to SXGA (1280 × 1024 at 75 Hz).
The AD9985 includes a 140 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and Hsync and COAST signals. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9985’s on-chip PLL generates a pixel clock from the
Hsync input. Pixel clock output frequencies range from 12 MHz
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
110 MSPS/140 MSPS Analog Interface for
to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the COAST signal is presented, the PLL maintains its
output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase
relationships are maintained. The AD9985 also offers full sync
processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by
the user through the CLAMP input pin. This interface is fully
programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9985 is
provided in a space-saving 80-lead LQFP surface-mount
plastic package and is specified over the –40°C to +85°C
temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
CLAMP
HSYNC
COAST
SOGIN
R
G
B
SDA
FILT
SCL
AIN
AIN
AIN
A0
FUNCTIONAL BLOCK DIAGRAM
CLAMP
CLAMP
CLAMP
SERIAL REGISTER AND
POWER MANAGEMENT
PROCESSING
GENERATION
AND CLOCK
LEVEL ADJUST
LEVEL ADJUST
LEVEL ADJUST
© 2004 Analog Devices, Inc. All rights reserved.
AUTO CLAMP
AUTO CLAMP
AUTO CLAMP
SYNC
Flat Panel Displays
Figure 1.
A/D
A/D
A/D
AD9985
REF
8
8
8
www.analog.com
AD9985
R
G
B
MIDSCV
DTACK
HSOUT
VSOUT
SOGOUT
REF
BYPASS
OUTA
OUTA
OUTA

Related parts for AD9985BSTZ-110

AD9985BSTZ-110 Summary of contents

Page 1

FEATURES Automated clamping level adjustment 140 MSPS maximum conversion rate 300 MHz analog bandwidth 0 1.0 V analog input range 500 ps p-p PLL clock jitter at 110 MSPS 3.3 V power supply Full sync processing Sync detect ...

Page 2

AD9985 TABLE OF CONTENTS Revision History ........................................................................... 2 Specifications..................................................................................... 3 Explanation of Test Levels........................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Design Guide................................................................................... 11 General Description................................................................... 11 Digital Inputs .............................................................................. 11 Input Signal ...

Page 3

SPECIFICATIONS Analog Interface 3 3.3 V, ADC clock = maximum conversion rate, unless otherwise noted Table 1. Parameter Temp RESOLUTION DC ACCURACY Differential Nonlinearity 25°C Full Integral Nonlinearity 25°C Full No Missing Codes ...

Page 4

AD9985 Parameter Temp DIGITAL OUTPUTS Output Voltage, High (V ) Full OH Output Voltage, Low (V ) Full OL Duty Cycle DATACK Full Output Coding POWER SUPPLY V Supply Voltage Full D V Supply Voltage Full DD P Supply Voltage ...

Page 5

... IV Full VI 2.5 Full VI Full V Full V 25°C V Full VI V −0.1 D Full VI Full IV 45 Rev Page AD9985 AD9985BSTZ-110 Typ Max Unit 8 Bits LSB ±0.5 +1.25/−1.0 LSB +1.5/−1.0 LSB ±0.5 ±1.85 LSB ±3.2 0.5 V p-p V p-p 100 ppm/°C 1 µA 2 µA ...

Page 6

... Full IV 2.2 Full IV 3.15 25°C V 25°C V 25°C V Full VI Full VI Full VI 25°C V 25°C V 25°C V 25°C V Full V Full Rev Page AD9985BSTZ-110 Typ Max Unit 3.3 3.45 V 3.3 3.45 V 3.3 3.45 V 132 525 760 16 300 MHz 2 ns 1.5 ...

Page 7

ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Analog Inputs VREF IN Digital Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high ...

Page 8

AD9985 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND GREEN <7> GREEN <6> GREEN <5> GREEN <4> GREEN <3> GREEN <2> GREEN <1> GREEN <0> GND BLUE <7> BLUE <6> BLUE <5> BLUE <4> BLUE <3> BLUE <2> BLUE <1> BLUE <0> ...

Page 9

Table 5. Pin Function Descriptions Pin Function Name OUTPUTS HSOUT Horizontal Sync Output A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be programmed via serial bus registers. By maintaining alignment ...

Page 10

AD9985 Pin Function Name SOGIN Sync-on-Green Input This input is provided to assist with processing signals with embedded sync, typically on the Green channel. The pin is connected to a high speed comparator with an internally generated threshold. The threshold ...

Page 11

DESIGN GUIDE GENERAL DESCRIPTION The AD9985 is a fully integrated solution for capturing analog RGB signals and digitizing them for display on flat-panel monitors or projectors. The circuit is ideal for providing a computer interface for HDTV monitors or as ...

Page 12

AD9985 input is present. The offset then remains in place when other signal levels are processed, and the entire signal is shifted to eliminate offset errors. In most PC graphics systems, black is transmitted between active video lines. With CRT ...

Page 13

ADC channels as well as any offset errors present on the incoming graphics or video signals. To activate the auto-offset mode, set Register 1Dh, Bit Next, the target code registers (19h through ...

Page 14

... Table 8 summarizes how the AD9985 determines what power mode and which circuitry is powered on/off in each of these modes. The power-down command has priority over the automatic circuitry. Table 8. Power-Down Mode Descriptions Mode Full- Power AD9985BSTZ Seek 12–30 Mode 30–60 60–110 Power- Down 1 Power-down is controlled via Bit 1 in serial bus Register 0FH ...

Page 15

... In some systems, however, Hsync is disturbed during the Vertical Sync period (Vsync). In some cases, Hsync pulses Rev Page AD9985 AD9985KSTZ AD9985BSTZ VCORNGE Current VCORNGE 00 110 00 ...

Page 16

AD9985 disappear. In other systems, such as those that employ Composite Sync (Csync) signals or embedded Sync-on-Green (SOG), Hsync includes equalization pulses or other distortions during Vsync. To avoid upsetting the clock generator during Vsync important to ignore ...

Page 17

Write and Hex Read or Default Address Read Only Bits Value 03H R/W 7:3 01****** **001*** 04H R/W 7:3 10000*** 05H 7:0 10000000 R/W 06H R/W 7:0 10000000 07H R/W 7:0 00100000 08H R/W 7:0 10000000 09H R/W 7:0 10000000 ...

Page 18

AD9985 Write and Hex Read or Default Address Read Only Bits Value *****0** ******0* *******0 11H R/W 7:0 00100000 12H R/W 7:0 00000000 13H R/W 7:0 00000000 14H RO 7:0 15H R/W 7:2 111111** 1 ******1* 0 *******1 16H R/W ...

Page 19

... A 5-bit value that adjusts the sampling phase in 32 steps across one pixel time. Each step represents an 11.25° shift in sampling phase. The power-up default value is 16. Rev Page AD9985 Pixel Clock Range (MHz) AD9985BSTZ 12–30 30–60 60–110 Current (µA) 50 100 150 ...

Page 20

AD9985 CLAMP TIMING 05 7–0 Clamp Placement An 8-bit register that sets the position of the internally generated clamp. When Clamp Function (Register 0FH, Bit clamp signal is generated internally position established by the ...

Page 21

MODE CONTROL Hsync Input Polarity Override This register is used to override the internal circuitry that determines the polarity of the Hsync signal going into the PLL. Table 13. Hsync Input Polarity Override Settings Override Bit Function ...

Page 22

AD9985 0F 7 Clamp Input Signal Source This bit determines the source of clamp timing. Table 21. Clamp Input Signal Source Settings Clamp Function Function 0 Internally Generated Clamp Signal 1 Externally Provided Clamp Signal A 0 enables the clamp ...

Page 23

Red Clamp Select This bit determines whether the Red channel is clamped to ground or to midscale. For RGB video, all three channels are referenced to ground. For YCbCr (or YUV), the Y channel is referenced to ground, ...

Page 24

AD9985 Table 33. Detected Hsync Input Polarity Status Hsync Polarity Result Status 0 Negative 1 Positive 14 4 Vsync Detect This bit is used to indicate when activity is detected on the Vsync input pin (Pin 31). If Vsync is ...

Page 25

Blue Target Code This specifies the targeted value of the final offset for the Blue channel when auto offset is employed (Register 0x1D Bit 7 = 1). Default Auto Offset Enable Enables the auto ...

Page 26

AD9985 2-WIRE SERIAL CONTROL PORT 2 A 2-wire serial control interface ( provided two AD9985 devices may be connected to the 2-wire serial interface, with each device having a unique address. The 2-wire serial interface comprises ...

Page 27

Data is read from the control registers of the AD9985 in a similar manner. Reading requires two data transfer operations: The base address must be written with the R/W bit of the slave address byte low to set up a ...

Page 28

AD9985 SYNC STRIPPER NEGATIVE PEAK SOG HSYNC IN ACTIVITY DETECT COAST VSYNC IN ACTIVITY DETECT Table 43. Control of the Sync Block Muxes via the Serial Register Serial Bus Mux No. Control Bit 1 and 2 0EH: Bit 3 3 ...

Page 29

PCB LAYOUT RECOMMENDATIONS The AD9985 is a high precision, high speed analog device. As such, to get the maximum performance from the part important to have a well laid out board. The following is a guide for designing ...

Page 30

AD9985 PLL Place the PLL loop filter components as close to the FILT pin as possible. Do not place any digital or other high frequency traces near these components. Use the values suggested in the data sheet with 10% tolerances ...

Page 31

... OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model 1 AD9985KSTZ-110 1 AD9985KSTZ-140 1 AD9985BSTZ-110 AD9985/PCB Pb-free part. 0.75 1.60 0.60 MAX 0. SEATING PLANE 10° 6° 0.20 2° 0.09 VIEW A 7° 20 3.5° 21 0° 0.10 MAX ...

Page 32

AD9985 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Patent Rights to use these components © ...

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