AD9985BSTZ-110 Analog Devices Inc, AD9985BSTZ-110 Datasheet - Page 22

• Manufacturer Part Number: AD9985BSTZ-110
• Description: IC,Data Acquisition Signal Conditioner,3-CHANNEL,8-BIT,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9985BSTZ-110

• Applications: Video
• Interface: Serial Port
• Voltage - Supply: 2.2 V ~ 3.45 V
• Package / Case: 80-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9985
0F
Table 21. Clamp Input Signal Source Settings
Clamp Function
0
1
0F
Table 22. Clamp Input Signal Polarity Settings
Clamp Function
1
0
0F
Table 23. Power-Down Settings
Select
0
1
0F
Table 24. Coast Input Polarity Override Settings
Override Bit
0
1
7
This bit determines the source of clamp timing.
A 0 enables the clamp timing circuitry controlled by
clamp placement and clamp duration. The clamp
position and duration is counted from the leading
edge of Hsync.
A 1 enables the external CLAMP input pin. The three
channels are clamped when the CLAMP signal is
active. The polarity of CLAMP is determined by the
Clamp Polarity bit (Register 0FH, Bit 6).
The power-up default value is Clamp Function = 0.
6
This bit determines the polarity of the externally
provided CLAMP signal.
Logic 1 means that the circuit will clamp when
CLAMP is low, and it will pass the signal to the ADC
when CLAMP is high.
Logic 0 means that the circuit will clamp when
CLAMP is high, and it will pass the signal to the ADC
when CLAMP is low.
The power-up default value is Clamp Polarity = 1.
5
This bit is used to select the active Coast source. The
choices are the Coast Input pin or Vsync. If Vsync is
selected, the additional decision of using the Vsync
input pin or the output from the sync separator needs
to be made (Register 0E, Bits 1, 0).
4
This register is used to override the internal circuitry
that determines the polarity of the Coast signal going
into the PLL.
Clamp Input Signal Source
Clamp Input Signal Polarity
Coast Select
Coast Input Polarity Override
Result
Coast Input Pin
Vsync (See above Text)
Result
Determined by Chip
Determined by User
Function
Active Low
Active High
Function
Internally Generated Clamp Signal
Externally Provided Clamp Signal
Rev. 0 | Page 22 of 32
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Table 25. Coast Input Polarity Settings
Coast Polarity
0
1
0F
Table 26. Seek Mode Override Settings
Select
1
0
0F
Table 27. Power-Down Settings
Select
0
1
10
The default for coast polarity override is 0.
3
This bit indicates the polarity of the Coast signal that
is applied to the PLL COAST input.
Active Low means that the clock generator will ignore
Hsync inputs when Coast is low, and continue
operating at the same nominal frequency until Coast
goes high.
Active High means that the clock generator will ignore
Hsync inputs when Coast is high, and continue
operating at the same nominal frequency until Coast
goes low.
This function needs to be used along with the Coast
Polarity Override bit (Bit 4).
The power-up default value is 1.
2
This bit is used to either allow or disallow the low
power mode. The low power mode (Seek Mode)
occurs when there are no signals on any of the Sync
inputs.
The default for this register is 1.
1
This bit is used to put the chip in full power-down. See
the Power Management section for details of which
blocks are powered down.
7-3
This register allows the comparator threshold of the
Sync-on-Green slicer to be adjusted. This register
adjusts it in steps of 10 mV, with the minimum setting
equaling 10 mV (11111) and the maximum setting
equaling 330 mV (00000).
The default setting is 23, which corresponds to a
threshold value of 100 mV; for a threshold of 150 mV,
the setting should be 18.
Coast Input Polarity
PWRDN
Seek Mode Override
Sync-on-Green Slicer Threshold
Result
Allow Seek Mode
Disallow Seek Mode
Function
Active Low
Active High
Result
Power-Down
Normal Operation