ADAU1590ACPZ-RL Analog Devices Inc, ADAU1590ACPZ-RL Datasheet - Page 18

• Manufacturer Part Number: ADAU1590ACPZ-RL
• Description: IC,Audio Amplifier,QUAD,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Class Dr

Specifications of ADAU1590ACPZ-RL

• Output Type: 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 15.5W x 2 @ 4 Ohm
• Voltage - Supply: 9 V ~ 15 V
• Features: Depop, Mute, Short-Circuit and Thermal Protection
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1590
POWER-UP/POWER-DOWN SEQUENCE
Figure 43 shows the recommended power-up sequence for the
ADAU1590.
The ADAU1590 has a special turn-on sequence that consists of
a fixed internal mute time during which the power stage does
not start switching. This internal mute time depends on the
master clock frequency and is 650 ms for a 24.576 MHz clock.
Also, the internal mute overrides the external MUTE and
ensures that the power stage does not switch on immediately
even if the external MUTE signal is pulled high in less than
650 ms after STDN . The power stage starts switching only
after 650 ms plus a small propagation delay of 200 μs has
elapsed and after MUTE is deasserted. Therefore, it is recom-
mended to ensure that t
during power-on.
Ensure that the MUTE signal is delayed by at least t
after STDN . This time is approximately 10 times the charging
time constant of the input coupling capacitor.
For example, if the input coupling capacitor is 4.7 μF, the time
constant is
Therefore, t
t
AVDD/2 before turning on the power stage.
When t
650 ms has elapsed after STDN (see Figure 44). However, note
that this method does not ensure pop-and-click suppression
because of less than recommended or insufficient t
WAIT
NOTES
1. INTERNAL MUTE IS INTERNAL TO CHIP.
STDN
INTERNAL MUTE
MUTE
OUTx+/OUTx–
AINx
t
t
t
INT
PDL-H
WAIT
T = R × C = 20 kΩ × 4.7 μF = 94 ms
is needed to ensure that the input capacitors are charged to
= 650ms @ 24.576MHz CLOCK
= 10 × R
WAIT
= 200µs
WAIT
< t
Figure 43. Recommended Power-Up Sequence
IN
INT
× C
= 10 × T = 940 ms ~ 1 sec.
, the power stage does not start switching until
IN
AVDD/DVDD
WAIT
PVDD
t
INT
> t
t
WAIT
INT
PVDD/2
to prevent the pop and click
AVDD/2
t
PDL-H
WAIT
WAIT
.
seconds
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The ADAU1590 uses three separate supplies: AVDD (3.3 V
analog for PGA and modulator), DVDD (3.3 V digital for
control logic and clock oscillator), and PVDD (9 V to 18 V
power stage and level shifter). Separate pins are provided for
the AVDD, DVDD, and PVDD supply connections, as well as
AGND, DGND, and PGND.
In addition, the ADAU1590 incorporates a built-in undervolt-
age lockout logic on DVDD as well as PVDD. This helps detect
undervoltage operation and eliminates the need to have an external
mechanism to sense the supplies.
The ADAU1590 monitors the DVDD and PVDD supply voltages
and prevents the power stage from turning on if either of the
supplies are not present or are below the operating threshold.
Therefore, if DVDD is missing or below the operating thresh-
old, for example, the power stage does not turn on, even if
PVDD is present, or vice versa.
Because this protection is only present on DVDD and PVDD
and not on AVDD, shorting both AVDD and DVDD externally
or generating AVDD and DVDD from one power source is
recommended. This ensures that both AVDD and DVDD
supplies are tracking each other and avoids the need to monitor
the sequence with respect to PVDD. This also ensures minimal
pop and click during power-up.
When using separate AVDD and DVDD supplies, ensure that
both supplies are stable before unmuting or turning on the
power stage.
Similarly, during shutdown, pulling MUTE to logic low before
pulling STDN down is recommended. However, where a fault
event occurs, the power stage shuts down to protect the part. In
this case, depending on the signal level, there is some pop at the
speaker.
STDN
INTERNAL MUTE
MUTE
OUTx+/OUTx–
AINx
t
t
NOTES
1. INTERNAL MUTE IS INTERNAL TO CHIP.
INT
WAIT
= 650ms @ 24.576MHz CLOCK
< T
INT
Figure 44. Power-Up Sequence, t
AVDD/DVDD
t
PVDD
WAIT
PVDD/2
t
INT
AVDD/2
WAIT
< t
INT