ADF4153BRUZ-RL Analog Devices Inc, ADF4153BRUZ-RL Datasheet - Page 21
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ADF4153BRUZ-RL
Manufacturer Part Number
ADF4153BRUZ-RL
Description
IC,FREQUENCY SYNTHESIZER,CMOS,TSSOP,16PIN,PLASTIC
Manufacturer
Analog Devices Inc
Type
Fractional N Synthesizer (RF)r
Datasheet
1.ADF4153BRUZ.pdf
(24 pages)
Specifications of ADF4153BRUZ-RL
Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:1
Differential - Input:output
Yes/No
Frequency - Max
4GHz
Divider/multiplier
No/Yes
Voltage - Supply
2.7 V ~ 3.3 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Frequency-max
4GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADF4153EBZ1 - BOARD EVAL FOR ADF4153
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADF4153BRUZ-RL7
Manufacturer:
ROHM
Quantity:
682
When operating in this mode, the maximum SCLOCK rate of
the ADuC812 is 4 MHz. This means that the maximum rate at
which the output frequency can be changed is 180 kHz.
ADSP-21xx Interface
Figure 19 shows the interface between the ADF4153 and the
ADSP-21xx digital signal processor. As discussed previously,
the ADF4153 needs a 24-bit serial word for each latch write.
The easiest way to accomplish this using the ADSP-21xx family
is to use the autobuffered transmit mode of operation with
alternate framing. This provides a means for transmitting an
entire block of serial data before an interrupt is generated.
Set up the word length for eight bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the three 8-bit bytes, enable the autobuffered mode, and
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
ADSP-21xx
I/O FLAGS
Figure 19. ADSP-21xx to ADF4153 Interface
SCLK
TFS
DT
CLK
DATA
LE
MUXOUT
(LOCK DETECT)
ADF4153
Rev. D | Page 21 of 24
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board (PCB) pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This ensures that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they should
be incorporated in the thermal pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and the
via barrel should be plated with one ounce of copper to plug the
via. The user should connect the PDB thermal pad to AGND.
ADF4153