ADG604YRUZ-REEL7 Analog Devices Inc, ADG604YRUZ-REEL7 Datasheet - Page 6
![IC,ANALOG MUX,QUAD,1-CHANNEL,CMOS,TSSOP,14PIN,PLASTIC](/photos/6/60/66047/ru-14_sml.jpg)
ADG604YRUZ-REEL7
Manufacturer Part Number
ADG604YRUZ-REEL7
Description
IC,ANALOG MUX,QUAD,1-CHANNEL,CMOS,TSSOP,14PIN,PLASTIC
Manufacturer
Analog Devices Inc
Type
Analog Multiplexerr
Datasheet
1.ADG604YRUZ.pdf
(12 pages)
Specifications of ADG604YRUZ-REEL7
Function
Multiplexer
Circuit
1 x 4:1
On-state Resistance
115 Ohm
Voltage Supply Source
Dual Supply
Voltage - Supply, Single/dual (±)
±2.7 V ~ 5.5 V
Current - Supply
0.001µA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP (0.173", 4.40mm Width)
Package
14TSSOP
Maximum On Resistance
460@2.7V Ohm
Maximum Propagation Delay Bus To Bus
100@±5V|150@5V|320@3V ns
Maximum High Level Output Current
10 mA
Multiplexer Architecture
4:1
Maximum Turn-off Time
160@3V ns
Maximum Turn-on Time
250@3V ns
Power Supply Type
Single|Dual
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADG604
V
V
GND
I
I
S
D
R
R
I
I
I
V
V
V
I
C
C
C
C
t
t
t
t
Charge Injection
Crosstalk
Off Isolation
Bandwidth
Insertion Loss
DD
SS
S
D
D
INL
ON
OFF
TRANSITION
BBM
R
DD
SS
ON
FLAT(ON)
D
INL
INH
S
D
D
IN
, I
(OFF)
(OFF)
, V
, C
ON
(OFF)
(OFF)
(EN)
S
(I
(EN)
(ON)
S
INH
S
(ON)
)
Most Positive Power Supply Potential
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to
ground at the device.
Ground (0 V) Reference
Positive Supply Current
Negative Supply Current
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Ohmic Resistance between D and S
On Resistance Match between any two channels, i.e., R
Flatness is defined as the difference between the maximum and minimum value of On resistance as measured
over the specified analog signal range.
Source Leakage Current with the Switch “OFF”
Drain Leakage Current with the Switch “OFF”
Channel Leakage Current with the Switch “ON”
Analog Voltage on Terminals D, S
Maximum Input Voltage for Logic “0”
Minimum Input Voltage for Logic “1”
Input Current of the Digital Input
Channel Input Capacitance for “OFF” Condition
Channel Output Capacitance for “OFF” Condition
“On” Switch Capacitance
Digital Input Capacitance
Delay time between the 50% and 90% points of the digital input and switch “ON” condition.
Delay time between the 50% and 90% points of the digital input and switch “OFF” condition.
Delay time between the 50% and 90% points of the digital input and switch “ON” condition when switching
from one address state to another.
“OFF” time or “ON” time measured between the 80% points of both switches, when switching from one address
state to another.
A measure of the glitch impulse transferred from the digital input to the analog output during switching.
A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance.
A measure of unwanted signal coupling through an “On” switch.
Frequency Response of the “On” Switch
Loss Due to the On Resistance of the Switch
TERMINOLOGY
ON
Max – R
ON
Min