ADM693ANZ Analog Devices Inc, ADM693ANZ Datasheet - Page 7

• Manufacturer Part Number: ADM693ANZ
• Description: IC,Power Supply Supervisor,CMOS,DIP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Battery Backup Circuitr

Specifications of ADM693ANZ

• Number Of Voltages Monitored: 1
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 35 ms Minimum
• Voltage - Threshold: 4.4V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. A
OSC SEL
Low
Low
Floating or High
Floating or High
NOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F
The watchdog timeout period is fixed at 1.6 seconds, and the
reset pulse width is fixed at 50 ms on the ADM690/ADM692.
On the ADM694 the watchdog timeout period is also 1.6 sec-
onds but the reset pulse width is fixed at 200 ms. The ADM691/
ADM693/ADM695 allow these times to be adjusted as shown
in Table I. Figure 4 shows the various oscillator configurations
which can be used to adjust the reset pulse width and watchdog
timeout period.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; while
with it connected low, the 100 ms timeout period is selected. In
either case, immediately after a reset, the timeout period is 1.6
seconds. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, then the 100 ms watchdog period be-
comes effective after the first transition of WDI. The software
should be written such that the I/O port driving WDI is left in
its power-up reset state until the initialization routines are com-
pleted and the microprocessor is able to toggle WDI at the mini-
mum watchdog timeout period of 70 ms.
Watchdog Output (WDO)
The Watchdog Output WDO (ADM691/ADM693/ADM695)
provides a status output which goes low if the watchdog timer
“times out” and remains low until set high by the next transition
on the Watchdog Input. WDO is also set high when V
below the reset threshold.
0 TO 250kHz
Figure 4a. External Clock Source
CLOCK
Table I. ADM691, ADM693, ADM695 Reset Pulse Width and Watchdog Timeout Selections
OSC IN
External Clock Input
External Capacitor
Low
Floating or High
8
7
OSC IN
OSC SEL
ADM691
ADM693
ADM695
Normal
1024 CLKS
260 ms
100 ms
1.6 s
Watchdog Timeout Period
CC
C/47 pF
goes
–7–
Immediately
After Reset
4096 CLKS
1.04 s
1.6 s
1.6 s
Figure 4c. Internal Oscillator (1.6 Second Watchdog)
Figure 4d. Internal Oscillator (100 ms Watchdog)
C/47 pF
NC
NC
NC
OSC
Figure 4b. External Capacitor
(Hz) = 184,000/C (pF).
ADM691/ADM693
512 CLKS
130 ms C/47 pF
50 ms
50 ms
C
OSC
Reset Active Period
8
7
8
7
8
7
OSC IN
OSC IN
OSC SEL
OSC SEL
OSC IN
OSC SEL
ADM690–ADM695
ADM691
ADM693
ADM695
ADM691
ADM693
ADM695
ADM691
ADM693
ADM695
ADM695
2048 CLKS
520 ms
200 ms
200 ms
C/47 pF