ADM802LARNZ-REEL Analog Devices Inc, ADM802LARNZ-REEL Datasheet - Page 5

• Manufacturer Part Number: ADM802LARNZ-REEL
• Description: 5V CMOS UP I.C.
• Manufacturer: Analog Devices Inc
• Type: Battery Backup Circuitr

Specifications of ADM802LARNZ-REEL

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.65V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER FAIL RESET, RESET
RESET is an active low output which provides a RESET signal
to the microprocessor whenever V
V
low. The nominal reset voltage threshold is 4.65 V (ADM690A/
ADM802L/ADM805L or 4.4 V ADM692A/ADM802M/
ADM805M.
On power-up RESET will remain low for 200 ms after V
above the reset threshold. This allows time for the power supply
and microprocessor to stabilize. On power-down, the RESET
output remains low with V
the microprocessor is held in a stable shutdown condition.
The guaranteed minimum and maximum thresholds are as follows:
ADM690A/ADM802L/ADM805L: 4.5 V and 4.75 V
ADM692A: 4.25 V and 4.5 V.
ADM802L: 4.55 V and 4.7 V
ADM802M: 4.3 V and 4.45 V
The ADM805L and ADM805M contain an active high reset
output. This is the complement of RESET and is intended for
processors requiring an active high RESET signal.
The guaranteed minimum and maximum thresholds for the
ADM805 are:
ADM805L: 4.5 V and 4.75 V
ADM805M: 4.25 V and 4.5 V.
Watchdog Timer RESET, RESET
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within
1.6 seconds, a RESET pulse is generated. The watchdog
timeout period restarts with each transition on the WDI pin. To
ensure that the watchdog timer does not time out, either a
high-to-low or low-to-high transition on the WDI pin must
occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be
issued after each timeout period (1.6 s). The watchdog monitor
can be deactivated by floating the Watchdog Input (WDI) or by
connecting it to midsupply.
REV. 0
CC
POWER FAIL
WATCHDOG
INPUT (WDI)
INPUT (PFI)
falls below the reset threshold, the RESET output is forced
V
BATT
V
CC
Figure 7. Functional Block Diagram
4.65V*
1.25V
*4.4V FOR ADM692A/ADM802M/ADM805M
TRANSITION DETECTOR
SWITCHOVER
WATCHDOG
BATTERY
(1.6s)
( ) = ADM805L/M ONLY
CC
as low as 1 V. This ensures that
GENERATOR
RESET
CC
is at an invalid level. When
ADM690A
ADM692A
ADM802L
ADM802M
ADM805L
ADM805M
(RESET)
V
RESET
POWER FAIL
OUTPUT (PFO)
OUT
CC
ADM690A/ADM692A/ADM802L/M/ADM805L/M
rises
–5–
BATTERY SWITCHOVER SECTION
During normal operation with V
threshold, V
PMOS transistor switch. This switch has a typical on-resistance
of less than 1
terminal. Once V
V
connects to V
and V
V
may require instantaneous currents of greater than 100 mA. If
this is the case, then a bypass capacitor should be connected to
V
RAM. A capacitance value of 0.1 F or greater may be used.
A 9
during battery backup. This MOSFET has very low input-to-
output differential (dropout voltage) at the low current levels
required for battery backup of CMOS RAM or other low power
CMOS circuitry. The supply current in battery backup is
typically 0.05 A.
Typically 3 V batteries are used as the backup supply. High
value capacitors, either standard electrolytic or the farad size
double layer capacitors, can also be used for short-term memory
back up. A small charging current of typically 10 nA (0.1 A
max) flows out of the V
maintaining rechargeable batteries in a fully charged condition.
This extends the life of the back up battery by compensating for
its self discharge current. Also note that this current poses no
problem when lithium batteries are used for back up since the
maximum charging current (0.1 A) is safe for even the smallest
lithium cells.
If the battery-switchover section is not used, V
connected to GND and V
CC
OUT
OUT
or V
. The capacitor will provide the peak current transients to the
RESET
RESET
BATT
is normally used to drive a RAM memory bank which
MOSFET switch connects the V
V
PFO
V
OUT
BATT
CC
+5V
+5V
+5V
+5V
is greater than V
0V
0V
0V
0V
0V
CC
is switched to V
OUT
3.0V
3.0V
is internally switched to V
and can supply up to 100 mA at the V
CC
Figure 8. Timing Diagram
only when V
falls below the reset threshold, the higher of
BATT
OUT
CC
terminal. This current is useful for
OUT
should be connected to V
.
CC
CC
. This means that V
is below the reset threshold
higher than the reset
BATT
t
RS
OUT
input to V
via an internal
BATT
V
BATT
should be
= PFI = 3.0V
BATT
OUT
OUT
CC
.