ADN4604ASVZ-RL Analog Devices Inc, ADN4604ASVZ-RL Datasheet - Page 17

• Manufacturer Part Number: ADN4604ASVZ-RL
• Description: 4.25Gbps 16x16 Crossbar Switch
• Manufacturer: Analog Devices Inc
• Series: XStream™r

Specifications of ADN4604ASVZ-RL

• Function: Crosspoint Switch
• Circuit: 1 x 16:16
• On-state Resistance: 56 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 2.7 V ~ 3.6 V
• Current - Supply: 95mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SWITCH CORE
The ADN4604 switch core is a fully nonblocking 16 × 16 array
that allows multicast and broadcast configurations. The config-
uration of the switch core is programmed through the serial
control interface. The crosspoint configuration map controls
the connectivity of the switch core. The crosspoint configuration
map consists of a double-rank register architecture where each
rank consists of an 8-byte configuration map as shown in
Figure 41. The second rank registers contain the current state of
the crosspoint. The first rank registers contain the next state.
Each entry in the connection map stores four bits per output,
which indicates which of the 16 inputs are connected to a given
output. An entire connectivity matrix can be programmed at
once by passing data from the first rank registers into the
second rank registers.
The first rank registers are two separate volatile 8-byte memory
banks which store connection configurations for the cross-
point. Map 0 is the default map and is located at Address 0x90
to Address 0x97. By default, Map 0 contains a diagonal
connection configuration whereby Input 15 is connected to
Output 0, Input 14 to Output 1, Input 13 to Output 2, and so
on. Similarly, by default, Map 1 contains the opposite diagonal
connection configuration where Input 0 is connected to output
0, Input 1 to Output 1, and so on. Both maps are read/write
accessible registers. The active map is selected by writing to
the XPT table select register (Address 0x81).
15
15
0
0
0
0
REGISTER 0x90 TO REGISTER 0x97
REGISTER 0x98 TO REGISTER 0x9F
FIRST RANK REGISTERS
XPT MAP 0
XPT MAP 1
OUTPUTS
OUTPUTS
15
15
Figure 41. Crosspoint Connection Map Block Diagram
REGISTER 0xB0 TO REGISTER 0xB7
REGISTER 0x81
MAP TABLE
SELECT
REGISTER 0x80
0
1
UPDATE PIN
Rev. 0 | Page 17 of 40
XPT STATUS READ
UPDATE
SECOND RANK REGISTERS
The crosspoint is configured by addressing the register
assigned to the desired output and writing the desired
connection data into the first rank of latches in either Map 0
or Map 1. The connection data is equivalent to the binary
coded value of the input number. This process is repeated until
each of the desired connections is programmed.
In situations where multiple outputs are to be programmed to
a single input, a broadcast command is available. A broadcast
command is issued by writing the binary value of the desired
input to the XPT broadcast register (Address 0x82). The broad-
cast is applied to the selected map as selected in the map table
select register (Address 0x81).
All output connections are updated simultaneously by passing
the data from the first rank of latches into the second rank by
writing 0x01 to the XPT update register (Address 0x80). This
is a write-only register. Alternatively, the UPDATE pin can be
strobed low. Otherwise, this pin should be left high.
The current state of the crosspoint connectivity is available
by reading the XPT status registers (Address 0xB0 to Address
0xB7). Register descriptions for the Map 0, Map 1 and XPT
status registers are provided in Table 9. A complete register
map is provided in Table 18.
15
0
0
XPT CORE
OUTPUTS
ADN4604
15