ADP1871ACPZ-1.0-R7 Analog Devices Inc, ADP1871ACPZ-1.0-R7 Datasheet - Page 6

• Manufacturer Part Number: ADP1871ACPZ-1.0-R7
• Description: 1.0MHz, Light Load Eff Enabled
• Manufacturer: Analog Devices Inc

Specifications of ADP1871ACPZ-1.0-R7

• Frequency - Max: 1MHz
• Pwm Type: Current Mode
• Number Of Outputs: 1
• Duty Cycle: 45%
• Voltage - Supply: 2.95 V ~ 20 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 10-WFDFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADP1871ACPZ-1.0-R7; ADP1871ACPZ-1.0-R7TR

ADP1870/ADP1871
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
VIN
COMP/EN
FB
GND
VREG
DRVL
PGND
DRVH
SW
BST
Description
High Input Voltage. Connect VIN to the drain of the upper-side MOSFET.
Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC.
Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground
plane (see the Layout Considerations section).
Internal Regulator Supply Bias Voltage for the ADP1870/ADP1871 Controller (Includes the Output Gate Drivers).
A bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF across VREG and GND are recommended.
VREG should not be loaded externally because it is intended to only bias internal circuitry.
Drive Output for the External Lower-Side, N-Channel MOSFET. This pin also serves as the current-sense gain
setting pin (see Figure 69).
Power GND. Ground for the lower-side gate driver and lower-side, N-channel MOSFET.
Drive Output for the External Upper-Side, N-Channel MOSFET.
Switch Node Connection.
Bootstrap for the Upper-Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected
between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be
connected between VREG and BST for increased gate drive capability.
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
COMP/EN
TO GROUND.
VREG
GND
VIN
FB
Figure 3. Pin Configuration
1
2
3
4
5
Rev. A | Page 6 of 44
(Not to Scale)
ADP1870/
ADP1871
TOP VIEW
10
9
8
7
6
BST
SW
DRVH
PGND
DRVL