ADSP-21060CZ-160 Analog Devices Inc, ADSP-21060CZ-160 Datasheet - Page 39
![Digital Signal Processor IC](/photos/6/71/67197/qs-240-2_sml.jpg)
ADSP-21060CZ-160
Manufacturer Part Number
ADSP-21060CZ-160
Description
Digital Signal Processor IC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Datasheet
1.ADSP-21062KSZ-133.pdf
(64 pages)
Specifications of ADSP-21060CZ-160
Peak Reflow Compatible (260 C)
No
Supply Voltage Max
5.25V
Dsp Type
Fixed / Floating Point
Leaded Process Compatible
No
Mounting Type
Surface Mount
Package / Case
240-MQFP
Interface
Host Interface, Link Port, Serial Port
Clock Rate
40MHz
Non-volatile Memory
External
On-chip Ram
512kB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21060CZ-160
Manufacturer:
AD
Quantity:
210
Company:
Part Number:
ADSP-21060CZ-160
Manufacturer:
AD31
Quantity:
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Company:
Part Number:
ADSP-21060CZ-160
Manufacturer:
Analog Devices Inc
Quantity:
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Part Number:
ADSP-21060CZ-160
Manufacturer:
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Quantity:
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Table 25. Link Port Service Request Interrupts:1u and 2u Speed Operations
1
Link Ports —2 × CLK Speed Operation
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path between
LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA relative to LCLK:
Table 26. Link Ports—Receive
1
2
3
4
Parameter
Timing Requirements
t
t
Only required for interrupt recognition in the current cycle.
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
t
For ADSP-21060L, specification is 5 ns min.
For ADSP-21062, specification is 4 ns min, for ADSP-21060LC, specification is 4.5 ns min.
LACK goes low with t
For ADSP-21060L, specification is 6 ns min, 18 ns max. For ADSP-21060C, specification is 6 ns min, 16.5 ns max. For ADSP-21060LC, specification is 6 ns min, 18.5 ns max.
SLCK
HLCK
SLDCL
HLDCL
LCLKIW
LCLKRWL
LCLKRWH
DLAHC
DLALC
Setup Skew = t
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period (2u Operation)
LCLK Width Low
LCLK Width High
LACK High Delay After CLKIN High
LACK Low Delay After LCLK High
LCLKTWH
DLALC
LACK/LCLK Setup Before CLKIN Low
LACK/LCLK Hold After CLKIN Low
relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.
min – t
1
2
DLDCH
– t
SLDCL
4
3
Rev. F | Page 39 of 64 | March 2008
1
1
Min
10
2
Min
2.5
t
4.5
4.25
18 + DT/2
6
2.25
CK
/2
Hold skew is the maximum delay that can be introduced in
LCLK relative to LDATA:
Calculations made directly from 2 speed specifications will
result in unrealistically small skew times because they include
multiple tester guardbands.
Note that link port transfers at 2× CLK speed at 40 MHz
(t
fers at 33 MHz (t
5 V
CK
Max
Hold Skew = t
5 V
= 25 ns) may fail. However, 2× CLK speed link port trans-
Max
28.5 + DT/2
16
CK
LCLKTWL
= 30 ns) work as specified.
Min
10
2
Min
2.25
2.25
t
5.25
4
18 + DT/2
6
CK
/2
min – t
HLDCH
3.3 V
3.3 V
Max
Max
29.5 + DT/2
16
– t
HLDCL
Unit
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns