ADSP-21062CSZ-160 Analog Devices Inc, ADSP-21062CSZ-160 Datasheet - Page 41
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ADSP-21062CSZ-160
Manufacturer Part Number
ADSP-21062CSZ-160
Description
IC,DSP,32-BIT,CMOS,QFP,240PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Specifications of ADSP-21062CSZ-160
Interface
Host Interface, Link Port, Serial Port
Clock Rate
40MHz
Non-volatile Memory
External
On-chip Ram
256kB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
240-MQFP, 240-PQFP
Device Core Size
32b
Architecture
Super Harvard
Format
Floating Point
Clock Freq (max)
40MHz
Mips
40
Device Input Clock Speed
40MHz
Ram Size
256KB
Program Memory Size
Not RequiredKB
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
MQFP
Package
240MQFP
Numeric And Arithmetic Format
Floating-Point
Maximum Speed
40 MHz
Device Million Instructions Per Second
40 MIPS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21062CSZ-160
Manufacturer:
AD
Quantity:
13 888
Company:
Part Number:
ADSP-21062CSZ-160
Manufacturer:
ADI20
Quantity:
93
Company:
Part Number:
ADSP-21062CSZ-160
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
TRANSMIT
LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION
RECEIVE
LACK (OUT)
LINK PORT INTERRUPT SETUP TIME
LDAT(3:0)
LDAT(3:0)
LACK (IN)
LDAT(3:0)
LCLK 1x
LCLK 2x
LCLK 1x
LCLK 2x
LCLK
LACK
CLKIN
CLKIN
CLKIN
CLKIN
OR
LCLK
LACK
OR
LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.
THE
t
t
SLACH
t
t
ENDLK
DLCLK
DLAHC
OUT
t
t
REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
HLDCH
LCLKTWH
t
DLDCH
t
LCLKRWH
t
LCLKTWL
t
SLCK
t
SLDCL
t
IN
HLCK
t
LCLKIW
TRANSMITTED
LAST NIBBLE
Rev. F | Page 41 of 64 | March 2008
t
HLDCL
Figure 24. Link Ports—Receive
t
t
SLACH
LCLKRWL
t
TDLK
TRANSMITTED
FIRST NIBBLE
t
HLACH
t
DLALC
LCLK INACTIVE
(HIGH)
t
DLACLK