ADSP-2189NBCAZ-320 Analog Devices Inc, ADSP-2189NBCAZ-320 Datasheet - Page 29

IC,DSP,16-BIT,CMOS,BGA,144PIN,PLASTIC

ADSP-2189NBCAZ-320

Manufacturer Part Number
ADSP-2189NBCAZ-320
Description
IC,DSP,16-BIT,CMOS,BGA,144PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet

Specifications of ADSP-2189NBCAZ-320

Interface
Host Interface, Serial Port
Clock Rate
80MHz
Non-volatile Memory
External
On-chip Ram
192kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.90V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-CSPBGA
Device Core Size
16b
Architecture
Enhanced Harvard
Format
Fixed Point
Clock Freq (max)
80MHz
Mips
80
Device Input Clock Speed
80MHz
Ram Size
192KB
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (min)
1.8V
Operating Supply Voltage (max)
2/3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-2189NBCAZ-320
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Interrupts and Flags
Table 16. Interrupts and Flags
1
2
3
4
5
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
If IRQx and FI inputs meet t
Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
Flag Outputs = PFx, FL0, FL1, FL2, FO.
IFS
IFH
FOH
FOD
following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-218x DSP Hardware Reference for further information on
interrupt servicing.)
IRQx, FI, or PFx Setup before CLKOUT Low
IRQx, FI, or PFx Hold after CLKOUT High
Flag Output Hold after CLKOUT Low
Flag Output Delay from CLKOUT Low
IFS
and t
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the
OUTPUTS
CLKOUT
FLAG
IRQx
PFx
FI
Rev. A | Page 29 of 48 | August 2006
5
5
Figure 27. Interrupts and Flags
1, 2, 3, 4
1, 2, 3, 4
t
FOH
t
FOD
t
IFH
t
IFS
Min
0.25t
0.25t
0.5t
CK
CK
CK
– 5
+ 10
Max
0.5t
CK
+ 4
ADSP-218xN
Unit
ns
ns
ns
ns

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