ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 24
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ADSP-BF514KSWZ-4F4
Manufacturer Part Number
ADSP-BF514KSWZ-4F4
Description
Low-Pwr BF Proc W/flash & Cnsmr Conctvty
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr
Datasheets
1.ADSP-BF531SBSTZ400.pdf
(12 pages)
2.ADSP-BF512KSWZ-3.pdf
(68 pages)
3.ADSP-BF514KSWZ-4F4.pdf
(72 pages)
Specifications of ADSP-BF514KSWZ-4F4
Interface
I²C, PPI, RSI, SPI, SPORT, UART/USART
Clock Rate
400MHz
Non-volatile Memory
FLASH (4Mbit)
On-chip Ram
116kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.30V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
Architecture
Modified Harvard
Format
Fixed Point
Clock Freq (max)
400MHz
Device Input Clock Speed
400MHz
Ram Size
48KB
Program Memory Size
1024KB
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
176
Package Type
LQFP EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-BF514KSWZ-4F4
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 10. Signal Descriptions
1
2
3
4
Signal Name
Port J
PJ0:SCL
PJ1:SDA
Real Time Clock
RTXI
RTXO
JTAG Port
TCK
TDO
TDI
TMS
TRST
EMU
Clock
CLKIN
XTAL
CLKBUF
Mode Controls
RESET
NMI
BMODE2-0
Voltage Regulation Interface
PG
EXT_WAKE
Power Supplies
V
V
V
V
V
V
V
GND
See
When driven low, the PF15 signal can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as PHYINT. If the pin/ball
Boot host wait is a GPIO signal toggled by the boot kernel. The mandatory external pull-up/pull-down resistor defines the signal polarity.
A pull-up resistor is required for the boot from external SPI EEPROM or flash (BMODE = 0x3).
is used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the signal with a resistor.
DDEXT
DDINT
DDRTC
DDFLASH
DDMEM
PPOTP
DDOTP
Output Drive Currents on Page 55
for more information about each driver type.
Type Function
I/O 5V TWI Serial Clock (This signal is an open-drain output and requires a pull-up
I/O 5V TWI Serial Data (This signal is an open-drain output and requires a pull-up
I
O
I
O
I
I
O
I
O
O
I
I
I
O
P
P
P
P
P
P
P
G
I
I
Rev. A | Page 24 of 72 | August 2010
resistor. Consult version 2.1 of the I
resistor. Consult version 2.1 of the I
RTC Crystal Input (This ball should be pulled low when not used.)
RTC Crystal Output (Does not three-state during hibernate)
JTAG Clock
JTAG Serial Data Out
JTAG Serial Data In
JTAG Mode Select
JTAG Reset (This signal should be pulled low if the JTAG port is not used.)
Emulation Output
Clock/Crystal Input
Crystal Output (If CLKBUF is enabled, does not three-state during hibernate)
Buffered XTAL Output (If enabled, does not three-state during hibernate)
Reset
Non-maskable Interrupt (This signal should be pulled high when not used.)
Boot Mode Strap 2-0
Power Good (This signal should be pulled low when not used.)
Wake up Indication (Does not three-state during hibernate)
ALL SUPPLIES MUST BE POWERED See
I/O Power Supply
Internal Power Supply
Real Time Clock Power Supply
Internal SPI Flash Power Supply
MEM Power Supply
OTP Programming Voltage
OTP Power Supply
Ground for All Supplies
2
2
C specification for the proper resistor value.)
C specification for the proper resistor value.)
Operating Conditions on Page
25.
E
E
C
C
C
F
Driver
Type
1