ADUC7126BSTZ126-RL Analog Devices Inc, ADUC7126BSTZ126-RL Datasheet
ADUC7126BSTZ126-RL
Specifications of ADUC7126BSTZ126-RL
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ADUC7126BSTZ126-RL Summary of contents
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FEATURES Analog input/output Multichannel, 12-bit, 1 MSPS ADC ADC channels Fully differential and single-ended modes analog input range REF 12-bit voltage output DACs 4 DAC outputs available On-chip voltage reference On-chip temperature sensor ...
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ADuC7124/ADuC7126 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications ..................................................................................... 5 Timing Specifications .................................................................. 8 Absolute Maximum Ratings .......................................................... 13 ESD Caution ................................................................................ 13 Pin ...
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REVISION HISTORY 1/11—Rev A to Rev B Change s to Table 1 ........................................................................... 5 10/10—Rev Rev. A Added ADuC7126 .............................................................. Universal Changes to Features Section ............................................................ 1 Moved Figure 1 .................................................................................. 1 Changes to Figure 1 ........................................................................... 1 ...
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ADuC7124/ADuC7126 GENERAL DESCRIPTION The ADuC7124/ADuC7126 are fully integrated, 1 MSPS, 12-bit data acquisition system incorporating high performance multichannel ADCs, 16-bit/32-bit MCUs, and Flash/EE memory on a single chip. The ADC consists single-ended inputs. An additional four ...
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SPECIFICATIONS AV = IOV = 2 3 2.5 V internal reference REF Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time Accuracy Resolution Integral Nonlinearity 3, 4 Differential Nonlinearity ...
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ADuC7124/ADuC7126 Parameter ANALOG OUTPUTS Output Voltage Range 0 Output Voltage Range 1 Output Voltage Range 2 Output Impedance DAC IN OP AMP MODE DAC Output Buffer in Op Amp Mode Input Offset Voltage Input Offset Voltage Drift Input Offset Current ...
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Parameter LOGIC INPUTS Input Low Voltage INL V , Input High Voltage INH LOGIC OUTPUTS V , Output High Voltage Output Low Voltage 11 OL CRYSTAL INPUTS XCLKI and XCLKO Logic Inputs, XCLKI Only ...
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ADuC7124/ADuC7126 Parameter ESD TESTS HBM Passed Up To FICDM Passed All ADC channel specifications are guaranteed during normal core operation. 2 Apply to all ADC input channels. 3 Measured using the factory-set default values in the ADC ...
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BUF SDATA (I/O) t DSU t PSU SCLK ( STOP START CONDITION CONDITION SPI Timing Table 4. SPI Master Mode Timing (Phase Mode = 1) Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse ...
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ADuC7124/ADuC7126 Table 5. SPI Master Mode Timing (Phase Mode = 0) Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data output setup before SCLOCK edge ...
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Table 6. SPI Slave Mode Timing (Phase Mode = 1) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data ...
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ADuC7124/ADuC7126 Table 7. SPI Slave Mode Timing (Phase Mode = 0) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t ...
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ABSOLUTE MAXIMUM RATINGS AGND = GND = DACGND = GND REF otherwise noted. Table 8. Parameter AV to IOV DD DD AGND to DGND IOV to IOGND AGND DD DD Digital Input Voltage to IOGND Digital Output Voltage ...
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ADuC7124/ADuC7126 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADCNEG DACGND DACV DD DAC0/ADC12 DAC1/ADC13 TMS TDI XCLKO XCLKI BM/P0.0/CMP /PLAI[7] OUT CONNECT NOTES 1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ...
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Pin No. Mnemonic 14 XCLKO 15 XCLKI 16 BM/P0.0/CMP /PLAI[7] OUT 17 DGND IOV DD 20 IOGND 21 P4.6/PLAO[14] 22 P4.7/PLAO[15] 23 P0.6/T1/MRST/PLAO[3] 24 TCK 25 TDO 26 P3.0/PWM0/PLAI[8] 27 P3.1/PWM1/PLAI[9] 28 P3.2/PWM2/PLAI[10] 29 P3.3/PWM3/PLAI[11] 30 ...
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ADuC7124/ADuC7126 Pin No. Mnemonic 35 IRQ1/P0.5/ADC /PLAO[2] BUSY 36 P2.0/SPM9/PLAO[5]/CONV START 37 P0.7/ECLK/XCLK/SPM8/PLAO[4]/SIN0 38 IOGND 39 IOV DD 40 P3.6/PWM /PLAI[14] TRIP 41 P3.7/PWM /PLAI[15] SYNC 42 P1.7/SPM7/DTR/SPICS /PLAO[0] 43 P1.6/SPM6/PLAI[6] 44 P4.0/PLAO[8]/SIN1 45 P4.1/PLAO[9]/SOUT1 46 P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3 47 P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2 48 ...
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Pin No. Mnemonic 50 P1.1/SPM1/SOUT0/I2C0SDA/PLAI[1] 51 P1.0/T1/SPM0/SIN0/I2C0SCL/PLAI[0] 52 P4.2/PLAO[10] 53 P4.3/PLAO[11] 54 P4.4/PLAO[12] 55 RTCK 56 V REF 57 DAC REF AGND 60 GND REF 61 ADC0 62 ADC1 63 ADC2/CMP0 64 ADC3/CMP1 Description General-Purpose Input ...
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ADuC7124/ADuC7126 ADC4 1 ADC5 2 ADC6 3 ADC7 4 ADC8 5 ADC9 6 ADC10 7 ADCNEG 8 DACGND 9 DACV ...
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Pin No. Mnemonic 11 DAC0/ADC12 12 DAC1/ADC13 13 DAC2/ADC14 14 DAC3/ADC15 15 TMS 16 TDI 17 P0.1/PWM4/BLE 18 XCLKO 19 XCLKI 20 BM/P0.0/CMP /PLAI[7]/MS0 OUT 21 DGND IOV DD 24 IOGND 25 P4.6/AD14/PLAO[14] 26 P4.7/AD15/PLAO[15] 27 ...
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ADuC7124/ADuC7126 Pin No. Mnemonic 34 P3.3/AD3/PWM3/PLAI[11] 35 P2.4/SPM13/PWM0/MS0/SOUT1 36 P0.3/TRST/A16/ADC BUSY 37 P2.5/PWM1/MS1 38 P2.6/PWM2/MS2 39 P3.4/AD4/PWM4/PLAI[12] 40 P3.5/AD5/PWM5/PLAI[13] 41 RST 42 IRQ0/P0.4/PWM /PLAO[1]/MS1 TRIP 43 IRQ1/P0.5/ADC /PLAO[2]/MS2 BUSY 44 P2.7/PWM3/MS3 45 P2.0/SPM9/PLAO[5]/ CONV START 46 P0.7/SPM8/ECLK/XCLK/PLAO[4]/SIN0 47 IOGND 48 ...
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Pin No. Mnemonic 49 P2.3/SPM12/AE/SIN1 50 P2.1/WS /PWM0/PLAO[6] 51 P2.2/RS /PWM1/PLAO[7] 52 P3.6/AD6/PWM /PLAI[14] TRIP 53 P3.7/AD7/PWM /PLAI[15] SYNC 54 P1.7/SPM7/DTR/SPICS /PLAO[0] 55 P1.6/SPM6/PLAI[6] 56 P4.0/SPM10/SIN1/AD8/PLAO[8] 57 P4.1/SPM11/SOUT1/AD9/PLAO[9] 58 P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3 59 P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2 60 P1.3/SPM3/CTS/I2C1SDA/PLAI[3] 61 P1.2/SPM2/RTS/I2C1SCL/PLAI[2] Description General-Purpose Input and ...
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ADuC7124/ADuC7126 Pin No. Mnemonic 62 P1.1/SPM1/SOUT0/I2C0SDA/PLAI[1] 63 P1.0/T1/SPM0/SIN0/I2C0SCL/PLAI[0] 64 P4.2/AD10/PLAO[10] 65 P4.3/AD11/PLAO[11] 66 P4.4/AD12/PLAO[12] 67 P4.5/AD13/PLAO[13]/RTCK 68 IOV DD 69 IOGND 70 V REF 71 DAC REF 73, 74 AGND 75 GND REF 76 ADC11 77 ADC0 ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0.3 0.2 0.1 0 –0.1 –0.2 ADC CODES Figure 9. Typical DNL Error, Temperature 25° Internal 2.5 V, Single-Ended Mode REF ADCCP = ADC0, ADCCN = ADC0, Sampling Rate = 345 kHz Worst Case Positive ...
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ADuC7124/ADuC7126 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 ADC CODES Figure 13. Typical DNL Error, Temperature 25° Internal 2.5 V, Single-Ended Mode REF ADCCP = ADC8, ADCCN = ADC0, Sampling Rate = 345 kHz Worst-Case Positive = ...
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SNR: 69.85dB 0 THD: –79.91dB PHSN: –82.93dB, 29.771kHz –20 –40 –60 –80 –100 –120 –140 0 50 100 FREQUENCY (kHz) Figure 17. SINAD, THD, and PHSN of ADC Internal 2.5 V, Single-Ended Mode REF ADCCP = ADC0 ...
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ADuC7124/ADuC7126 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity (INL) The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below ...
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OVERVIEW OF THE ARM7TDMI CORE The ARM7® core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be eight bits, 16 bits bits. ...
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ADuC7124/ADuC7126 More information relative to the model of the programmer and the ARM7TDMI core architecture can be found in the following materials from ARM: • DDI0029G, ARM7TDMI Technical Reference Manual • DDI-0100, ARM Architecture Reference Manual INTERRUPT LATENCY The worst-case ...
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MEMORY ORGANIZATION The ADuC7124/ADuC7126 incorporate three separate blocks of memory SRAM and two 64 kB blocks of on-chip Flash/EE memory. There are 126 kB of on-chip Flash/EE memory available to the user, and the remaining 2 kB ...
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ADuC7124/ADuC7126 0xFFFFFFFF FLASH CONTROL INTERFACE 1 0xFFFFF880 FLASH CONTROL INTERFACE 0 0xFFFFF800 GPIO 0xFFFFF400 EXTERNAL MEMORY 0xFFFFF000 PWM 0xFFFF0F80 PLA 0xFFFF0B00 SPI 0xFFFF0A00 I2C1 0xFFFF0900 I2C0 0xFFFF0800 UART1 0xFFFF0740 UART0 0xFFFF0700 DAC 0xFFFF0600 ADC 0xFFFF0500 BAND GAP REFERENCE 0xFFFF048C POWER ...
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Table 11. IRQ Base Address = 0xFFFF0000 Address 0xFFFF0000 0xFFFF0004 0xFFFF0008 0xFFFF000C 0xFFFF0010 0xFFFF0014 0xFFFF001C 0xFFFF0020 0xFFFF0024 0xFFFF0028 0xFFFF002C 0xFFFF0030 0xFFFF0034 0xFFFF0038 0xFFFF003C 0xFFFF0100 0xFFFF0104 0xFFFF0108 0xFFFF010C 0xFFFF011C 0xFFFF013C Table 12. System Control Base Address = 0xFFFF0200 Address 0xFFFF0220 0xFFFF0230 ...
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ADuC7124/ADuC7126 Table 14. PLL/PSM Base Address = 0xFFFF0400 Address 0xFFFF0404 0xFFFF0408 0xFFFF040C 0xFFFF0410 0xFFFF0414 0xFFFF0418 0xFFFF0434 0xFFFF0438 0xFFFF043C Table 15. PSM Base Address = 0xFFFF0440 Address 0xFFFF0440 0xFFFF0444 Table 16. Reference Base Address = 0xFFFF0480 Address 0xFFFF048C Table 17. ADC ...
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Table 19. UART0 Base Address = 0xFFFF0700 Address Name 0xFFFF0700 COM0TX 0xFFFF0700 COM0RX 0xFFFF0700 COM0DIV0 0xFFFF0704 COM0IEN0 0xFFFF0704 COM0DIV1 0xFFFF0708 COM0IID0 0xFFFF0708 COM0FCR COM0CON0 0xFFFF070C 0xFFFF0710 COM0CON1 0xFFFF0714 COM0STA0 0xFFFF0718 COM0STA1 0xFFFF072C COM0DIV2 Table 20. UART1 Base Address = 0xFFFF0740 ...
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ADuC7124/ADuC7126 Table 22. I2C1 Base Address = 0xFFFF0900 Address Name 0xFFFF0900 I2C1MCON 0xFFFF0904 I2C1MSTA 0xFFFF0908 I2C1MRX 0xFFFF090C I2C1MTX 0xFFFF0910 I2C1MCNT0 0xFFFF0914 I2C1MCNT1 0xFFFF0918 I2C1ADR0 0xFFFF091C I2C1ADR1 0xFFFF0924 I2C1DIV 0xFFFF0928 I2C1SCON 0xFFFF092C I2C1SSTA 0xFFFF0930 I2C1SRX 0xFFFF0934 I2C1STX 0xFFFF0938 I2C1ALT 0xFFFF093C I2C1ID0 ...
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Table 25. PWM Base Address = 0xFFFF0F80 Address Name 0xFFFF0F80 PWMCON0 0xFFFF0F84 PWM0COM0 0xFFFF0F88 PWM0COM1 0xFFFF0F8C PWM0COM2 0xFFFF0F90 PWM0LEN 0xFFFF0F94 PWM1COM0 0xFFFF0F98 PWM1COM1 0xFFFF0F9C PWM1COM2 0xFFFF0FA0 PWM1LEN 0xFFFF0FA4 PWM2COM0 0xFFFF0FA8 PWM2COM1 0xFFFF0FAC PWM2COM2 0xFFFF0FB0 PWM2LEN 0xFFFF0FB4 PWMCON1 0xFFFF0FB8 PWMCLRI Table ...
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ADuC7124/ADuC7126 Table 27. GPIO Base Address = 0xFFFF0400 Address Name 0xFFFFF400 GP0CON 0xFFFFF404 GP1CON 0xFFFFF408 GP2CON 0xFFFFF40C GP3CON 0xFFFFF410 GP4CON 0xFFFFF420 GP0DAT 0xFFFFF424 GP0SET 0xFFFFF428 GP0CLR 0xFFFFF42C GP0PAR 0xFFFFF430 GP1DAT 0xFFFFF434 GP1SET 0xFFFFF438 GP1CLR 0xFFFFF43C GP1PAR 0xFFFFF440 GP2DAT 0xFFFFF444 GP2SET ...
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ADC CIRCUIT OVERVIEW The analog-to-digital converter is a fast, multichannel, 12-bit ADC. It can operate from 2 3.6 V supplies and is capable of providing a throughput MSPS when the clock source is 41.78 ...
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ADuC7124/ADuC7126 TYPICAL OPERATION Once configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 12-bit result in the ADC data register. The top four bits are the sign bits. The 12-bit result ...
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Bit Value Description [2:0] Conversion type. 000 Enable CONV pin as a conversion input. START 001 Enable Timer1 as a conversion input. 010 Enable Timer0 as a conversion input. 011 Single software conversion. Sets to 000 after conversion (note that ...
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ADuC7124/ADuC7126 on P0.5 (see the General-Purpose Input/Output section) if enabled in the ADCCON register. ADCDAT Register Name: ADCDAT Address: 0xFFFF0510 Default Value: 0x00000000 Access: Read only ADCDAT is an ADC data result register that holds the 12-bit ADC result, as ...
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Single-Ended Mode In single-ended mode, SW2 is always connected internally to ground. The V pin can be floating. The input signal range on IN− IN+ REF CHANNEL+ AIN0 A SW1 ...
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ADuC7124/ADuC7126 CALIBRATION By default, the factory-set values written to the ADC offset (ADCOF) and gain coefficient registers (ADCGN) yield opti- mum performance in terms of end-point errors and linearity for standalone operation of the part (see the Specifications section). If ...
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TEMPREF Register Name: TEMPREF Address: 0xFFFF0548 Default Value: 0xXXXX Access: Read/write Table 35. TEMPREF MMR Bit Descriptions Bit Description [15:9] Reserved. 8 Temperature reference voltage sign bit. [7:0] Temperature sensor offset calibration voltage. To calculate the V from the TEMPREF ...
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... AN-724 application note describes the UART download protocol. Downloading (In-Circuit Programming) via I The ADuC7126BSTZ126I and ADuC7126BSTZ126IRL models facilitate code download via the the I download mode after a reset or power cycle if the BM pin is pulled low through an external 1 kΩ resistor and Flash Address 0x80014 = 0xFFFFFFFF ...
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Analog Devices, Inc. This board connects to the USB port and to the I ADuC7126. The part number is USB-I2C/LIN-CONV-Z. The AN-806 Application Note describes the protocol for serial 2 downloading via ...
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ADuC7124/ADuC7126 Table 45. FEE1STA Register Name Address Default Value FEE1STA 0xFFFFF880 0x0000 Table 46. FEE1MOD Register Name Address Default Value FEE1MOD 0xFFFFF884 0x80 Table 47. FEE1CON Register Name Address Default Value FEE1CON 0xFFFFF888 0x00 Table 48. FEE1DAT Register Name Address ...
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Table 54. FEExMOD MMR Bit Descriptions Bit Description [7:5] Reserved. 4 Flash/EE interrupt enable. Set by the user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete. Cleared by the user to disable the Flash/EE interrupt. ...
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ADuC7124/ADuC7126 Table 56. FEE0PRO and FEE0HID MMR Bit Descriptions Bit Description 31 Read protection. Cleared by the user to protect Block 0. Set by the user to allow reading of Block 0. [30:0] Write protection for Page 123 to Page ...
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Table 59. REMAP MMR Bit Descriptions (Address = 0xFFFF0220. Default Value = 0x00) Bit Name Description 0 Remap Remap bit. Set by the user to remap the SRAM to Address 0x00000000. Cleared automatically after reset to remap the Flash/EE memory ...
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ADuC7124/ADuC7126 RSTKEY0 Register Name: RSTKEY0 Address: 0xFFFF0248 Default Value: N/A Access Write only RSTKEY1 Register Name: RSTKEY1 Address: 0xFFFF0250 Default Value: N/A Access: Write only Rev Page 50 of 104 ...
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OTHER ANALOG PERIPHERALS DAC The ADuC7124/ADuC7126 incorporate two, or four, 12-bit voltage output DACs on chip, depending on the model. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. Each DAC has three selectable ranges: ...
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ADuC7124/ADuC7126 – 100mV DD 100mV 0x00000000 Figure 42. Endpoint Nonlinearities Due to Amplifier Saturation The endpoint nonlinearities conceptually illustrated in Figure 42 becomes worse as a function of output loading. Most of the ADuC7124/ADuC7126 data sheet specifications ...
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DACBKEY1 Register Name: DACBKEY1 Address: 0xFFFF0650 Default Value: 0x0000 Access: Write DACBKEY2 Register Name: DACBKEY2 Address: 0xFFFF0658 Default Value: 0x0000 Access: Write POWER SUPPLY MONITOR The power supply monitor regulates the IOV ADuC7124/ADuC7126. It indicates when the IOV drops below ...
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ADuC7124/ADuC7126 Comparator Interface The comparator interface consists of a 16-bit MMR, CMPCON, which is described in Table 69. CMPCON Register Name: CMPCON Address: 0xFFFF0444 Default Value: 0x0000 Access: Read/write Table 69. CMPCON MMR Bit Descriptions Bit Value Name Description [15:11] ...
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External Crystal Selection To switch to an external crystal, the user must follow this procedure: 1. Enable the Timer2 interrupt and configure it for a timeout period of >120 µs. 2. Follow the write sequence to the PLLCON register, setting ...
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ADuC7124/ADuC7126 MMRs and Keys The operating mode, clocking mode, and programmable clock divider are controlled via three MMRs, PLLCON (see Table 73), and POWCONx. PLLCON controls the operating mode of the clock system, POWCON0 controls the core clock frequency and ...
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Table 77. POWCON1 MMR Bit Descriptions Bit Value Name [15:12 PWMPO [10:9] 00 PWMCLKDIV 8 SPIPO [7:6] SPICLKDIV I2C1PO [4:3] I2C1CLKDIV I2C0PO [1:0] I2C0CLKDIV ...
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ADuC7124/ADuC7126 DIGITAL PERIPHERAL GENERAL-PURPOSE INPUT/OUTPUT The ADuC7124/ADuC7126 provide 40 general-purpose, bidirec- tional I/O (GPIO) pins. All I/O pins are 5 V tolerant, meaning the GPIOs support an input voltage general, many of the GPIO pins have ...
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Table 79. GPxCON Registers Name Address Default Value GP0CON 0xFFFFF400 0x00000000 GP1CON 0xFFFFF404 0x00000000 GP2CON 0xFFFFF408 0x00000000 GP3CON 0xFFFFF40C 0x00000000 GP4CON 0xFFFFF410 0x00000000 GPxCON are the Port x control registers that select the function of each pin of Port x, ...
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ADuC7124/ADuC7126 The drive strength bits can be written only once after reset. Additional writing to related bits has no effect on drive strength. The GPIO drive strength and pull-up disable are not always adjustable for GPIO port. Some control bits ...
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Baud Rate Generation There are two ways of generating the UART baud rate, using normal 450 UART baud rate generation and using the fractional divider. Normal 450 UART Baud Rate Generation The baud rate is a divided version of the ...
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ADuC7124/ADuC7126 COM1DIV0 Register Name: COM1DIV0 Address: 0xFFFF0740 Default Value: 0x00 Access: Read/write COM1DIV0 is a low byte divisor latch for UART1. COM1TX, COM1RX, and COM1DIV0 share the same address location. COM1TX and COM1RX can be accessed when Bit 7 in ...
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Table 93. COMxIID0 MMR Bit Descriptions Bit Name Description [7:6] FIFOMODE FIFO mode flag. 0x0: non-FIFO mode. 0x1: reserved. 0x2: reserved. 0x3: FIFO mode. Set automatically if FIFOEN is set. [5:4] Reserved [3:1] STATUS[2:0] Interrupt status bits that work only ...
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ADuC7124/ADuC7126 COM1CON0 Register Name: COM1CON0 Address: 0xFFFF074C Default Value: 0x00 Access: Read/write COM1CON0 is the line control register for UART1. Table 95. COMxCON0 MMR Bit Descriptions Bit Name Description 7 DLAB Divisor latch access. Set by the user to enable ...
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COM1STA0 Register Name: COM1STA0 Address: 0xFFFF0754 Default Value: 0xE0 Access: Read only COM1STA0 is the line status register for UART1. Table 97. COMxSTA0 MMR Bit Descriptions Bit Name Description 11 RX_error Set automatically if PE, FE set. ...
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ADuC7124/ADuC7126 COM0DIV2 Register Name: COM0DIV2 Address: 0xFFFF072C Default Value: 0x0000 Access: Read/write COM0DIV2 is a 16-bit fractional baud divide register for UART0. COM1DIV2 Register Name: COM1DIV2 Address: 0xFFFF076C Default Value: 0x0000 Access: Read/write COM1DIV2 is a 16-bit fractional baud divide ...
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SPI Registers The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON. SPI Status Register Name: SPISTA Address: 0xFFFF0A00 Default Value: 0x0000 Access: Read only Function: This 32-bit MMR contains the status of the SPI interface ...
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ADuC7124/ADuC7126 SPIRX Register Name: SPIRX Address: 0xFFFF0A04 Default Value: 0x00 Access: Read only Function: This 8-bit MMR is the SPI receive register. SPITX Register Name: SPITX Address: 0xFFFF0A08 Default Value: 0x00 Access: Write only Function: This 8-bit MMR is the ...
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Bit Name Description 9 SPIOEN Slave MISO output enable bit. Set this bit for MISO to operate as normal. Clear this bit to disable the output driver on the MISO pin. The MISO pin is open-drain when this bit is ...
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ADuC7124/ADuC7126 The ADuC7124/ADuC7126 incorporate two I that can be configured as a fully I 2 C-compatible I 2 device fully I C bus compatible slave device. Both I channels are identical. Therefore, the following ...
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Master Mode In master mode, the I2CxADR0 register is programmed with the address of the device. In 7-bit address mode, I2CxADR0[7:1] are set to the device address. I2CxADR0[0] is the read/write bit. In 10-bit address mode, the ...
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ADuC7124/ADuC7126 Master Status Register Name: I2C0MSTA, I2C1MSTA Address: 0xFFFF0804, 0xFFFF0904 Default Value: 0x0000, 0x0000 Access: Read only Function: This 16-bit MMR is the I Table 103. I2CxMSTA MMR Bit Descriptions Bit Name Description [15:11] Reserved ...
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I C Master Receive Register Name: I2C0MRX, I2C1MRX Address: 0xFFFF0808, 0xFFFF0908 Default Value: 0x00 Access: Read only Function: This 8-bit MMR is the I register Master Transmit Register Name: I2C0MTX, I2C1MTX Address: 0xFFFF080C 0xFFFF090C Default Value: ...
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ADuC7124/ADuC7126 Address 1 Register Name: I2C0ADR1, I2C1ADR1 Address: 0xFFFF081C, 0xFFFF091C Default Value: 0x00 Access: Read/write Function: This 8-bit MMR is used in 10-bit addressing mode only. This register contains the least significant byte of the address. Table ...
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Bit Name Description 2 5 I2CSETEN I C early transmit interrupt enable bit. Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit transmission. Clear this bit to enable a transmit ...
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ADuC7124/ADuC7126 Bit Name Description 2 [12:11] I2CID[1: address matching register. These bits indicate which I2CxIDx register matches the received address. [00] = received address matches I2CxID0. [01] = received address matches I2CxID1. [10] = received address matches I2CxID2. ...
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I C Slave Receive Registers Name: I2C0SRX, I2C1SRX Address: 0xFFFF0830, 0xFFFF0930 Default Value: 0x00 Access: Read Function: This 8-bit MMR is the Slave Transmit Registers Name: I2C0STX, I2C1STX Address: 0xFFFF0834, 0xFFFF0934 Default Value: 0x00 Access: ...
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ADuC7124/ADuC7126 PWM GENERAL OVERVIEW The ADuC7124/ADuC7126 integrate a 6-channel PWM interface (PWM0 to PWM5). The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default to H-bridge ...
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Table 113. PWMCON0 MMR Bit Descriptions Bit Name Description 14 SYNC Enables PWM synchronization. Set the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on ...
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ADuC7124/ADuC7126 Table 114. PWM Output Selection, HMODE = 1 1 PWMCON0 MMR ENA HOFF POINV DIR PWM0 PWM1 ...
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PROGRAMMABLE LOGIC ARRAY (PLA) Every ADuC7124/ADuC7126 integrates a fully programmable logic array (PLA) that consists of two independent but interconnected PLA blocks. Each block consists of eight PLA elements, giving each part a total of 16 PLA elements. Each PLA ...
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ADuC7124/ADuC7126 PLACLK Register Name: PLACLK Address: 0xFFFF0B40 Default Value: 0x00 Access: Read/write PLACLK is the clock selection for the flip-flops of Block 0 and Block 1. Note that the maximum frequency when using the GPIO pins as the clock input ...
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PLAADC Register Name: PLAADC Address: 0xFFFF0B48 Default Value: 0x00000000 Access: Read/write PLAADC is the PLA source for the ADC start conversion signal. Table 123. PLAADC MMR Bit Descriptions Bit Value Description [31:5] Reserved. 4 ADC start conversion enable bit. Set ...
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ADuC7124/ADuC7126 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 25 interrupt sources on the ADuC7124/ADuC7126 that are controlled by the interrupt controller. All interrupts are generated from the on-chip peripherals, except for the software interrupt (SWI), which is programmable by the ...
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IRQEN Register IRQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an IRQ exception. When a bit is set to 0, the correspond- ing source ...
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ADuC7124/ADuC7126 FIQCLR Register Name: FIQCLR Address: 0xFFFF010C Default Value: 0x00000000 Access: Write only FIQSTA FIQSTA is a read-only register that provides the current enabled FIQ source status (effectively a logic AND of the FIQSIG and FIQEN bits). When set to ...
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IRQVEC Register The IRQ interrupt vector register, IRQVEC points to a memory address containing a pointer to the interrupt service routine of the currently active IRQ. This register should only be read when an IRQ occurs and IRQ interrupt nesting ...
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ADuC7124/ADuC7126 IRQP2 Register Name: IRQP2 Address: 0xFFFF0028 Default Value: 0x00000000 Access: Read/write Table 132. IRQP2 MMR Bit Descriptions Bit Name Description 31 Reserved. [30:28] IRQ3PI A priority level can be set for IRQ3. 27 Reserved. [26:24] ...
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FIQVEC Register The FIQ interrupt vector register, FIQVEC, points to a memory address containing a pointer to the interrupt service routine of the currently active FIQ. This register should be read only when an FIQ occurs and FIQ interrupt nesting ...
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ADuC7124/ADuC7126 Bit Value Name [7:6] 11 IRQ2SRC[1: [5:4] 11 PLA0SRC[1: [3:2] 11 IRQ1SRC[1: [1:0] 11 IRQ0SRC[1: IRQCLRE Register Name: IRQCLRE Address: 0xFFFF0038 Default Value: 0x00000000 Access: Write only ...
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TIMERS The ADuC7124/ADuC7126 have four general-purpose timers/counters. • Timer0 • Timer1 • Timer2 or wake-up timer • Timer3 or watchdog timer These four timers in their normal mode of operation can be either free running or periodic. In free-running mode, ...
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ADuC7124/ADuC7126 Table 140. T0CON MMR Bit Descriptions Bit Value Description [31:8] Reserved. 7 Timer0 enable bit. Set by the user to enable Timer0. Cleared by the user to disable Timer0 by default. 6 Timer0 mode. Set by the user to ...
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Table 141. T1CON MMR Bit Descriptions Bit Value Description [31:18] Reserved. 17 Event select bit. Set by the user to enable time capture of an event. Cleared by the user to disable time capture of an event. [16:12] Event select ...
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ADuC7124/ADuC7126 Timer2 Value Register Name: T2VAL Address: 0xFFFF0344 Default Value: 0x0000 Access: Read only T2VAL is a 32-bit register that holds the current value of Timer2. Table 143. T2CON MMR Bit Descriptions Bit Value Description [31:11] Reserved. 10:9] Clock source ...
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Timer3 (Watchdog Time) Timer3 has two modes of operation: normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. Once enabled, it requires periodic servicing to prevent it from forcing a processor reset. ...
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ADuC7124/ADuC7126 T3CLRI Register Name: T3CLRI Address: 0xFFFF036C Default Value: 0x00 Access: Write only T3CLRI is an 8-bit register. Writing any value to this register on successive occassions clears the Timer3 interrupt in normal mode or resets a new timeout period ...
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XMCFG Register Name: XMCFG Address: 0xFFFFF000 Default Value: 0x00 Access: Read/write XMCFG is set enable external memory access. This must be set to 1 before any port pins can function as external memory access pins. The port ...
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ADuC7124/ADuC7126 MCLK AD[15:0] MSx AE RS MCLK AD[15:0] MSx AE RS Figure 59. External Memory Read Cycle with Address Hold and Bus Turn Cycles ADDRESS Figure 58. External Memory Read Cycle ADDRESS EXTRA ADDRESS HOLD TIME XMxPAR (BIT 10) BUS ...
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MCLK AD[15:0] ADDRESS EXTRA ADDRESS HOLD TIME (BIT 10) MSx AE WS Figure 60. External Memory Write Cycle with Address and Write Hold Cycles MCLK AD[15:0] ADDRESS MSx AE 1 ADDRESS WAIT STATE (BIT 14 TO BIT 12) WS Figure ...
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ADuC7124/ADuC7126 HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES The ADuC7124/ADuC7126 operational power supply voltage range is 2 3.6 V. Separate analog and digital power supply pins (AV and IOV , respectively) allow relatively free of noisy digital ...
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GROUNDING AND BOARD LAYOUT RECOMMENDATIONS As with all high resolution data converters, special attention must be paid to grounding and PC board layout of the ADuC7124/ADuC7126-based designs to achieve optimum performance from the ADCs and DAC. Although the part has ...
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ADuC7124/ADuC7126 POWER-ON RESET OPERATION An internal power-on reset (POR) is implemented on the ADuC7124/ADuC7126. For LV below 2.40 V typical, the DD internal POR holds the part in reset internal timer times out for typically 128 ms ...
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OUTLINE DIMENSIONS BSC SQ PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW 9.00 0.60 MAX 0.60 MAX 49 48 8.75 TOP BSC SQ VIEW 0.50 0.40 ...
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... ORDERING GUIDE ADC DAC 1 Model Channels Channels ADuC7124BCPZ126 10 2 ADuC7124BCPZ126- ADuC7126BSTZ126 12 4 ADuC7126BSTZ126- ADuC7126BSTZ126I 12 4 ADuC7126BSTZ126IRL 12 4 EVAL-ADuC7124QSPZ EVAL-ADuC7126QSPZ RoHS Compliant Part refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...