ADUC7126BSTZ126-RL Analog Devices Inc, ADUC7126BSTZ126-RL Datasheet - Page 73
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ADUC7126BSTZ126-RL
Manufacturer Part Number
ADUC7126BSTZ126-RL
Description
ARM7 With 12-Bit ADC & DACs, 128kB Flash
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.ADUC7126BSTZ126.pdf
(104 pages)
Specifications of ADUC7126BSTZ126-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
41.78MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
40
Program Memory Size
126KB (126K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADUC7126BSTZ126-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
I
Name:
Address:
Default Value:
Access:
Function:
I
Name:
Address:
Default Value:
Access:
Function:
I
Name:
Address:
Default Value:
Access:
Function:
Table 104. I2CxMCNT0 MMR Bit Descriptions
Bit
[15:9]
8
[7:0]
2
2
2
C Master Receive Register
C Master Transmit Register
C Master Read Count Register
Name
I2CRECNT
I2CRCNT
I2C0MRX, I2C1MRX
0xFFFF0808, 0xFFFF0908
0x00
Read only
This 8-bit MMR is the I
register.
I2C0MTX, I2C1MTX
0xFFFF080C 0xFFFF090C
0x00, 0x00
Read/write
This 8-bit MMR is the I
register.
I2C0MCNT0, I2C1MCNT0
0xFFFF0810, 0xFFFF0910
0x0000, 0x0000
Read/write
This 16-bit MMR holds the required number
of bytes when the master begins a read
sequence from a slave device.
Description
Reserved.
Set this bit if more than 256 bytes are
required from the slave.
Clear this bit when reading 256 bytes or
less.
These eight bits hold the number of bytes
required during a slave read sequence,
minus 1. If only a single byte is required,
these bits should be set to 0.
2
2
C master receive
C master transmit
Rev. B | Page 73 of 104
I
Name:
Address:
Default Value:
Access:
Function:
I
Name:
Address:
Default Value:
Access:
Function:
Table 105. I2CxADR0 MMR in 7-Bit Address Mode
Bit
[7:1]
0
Table 106. I2CxADR0 MMR in 10-Bit Address Mode
Bit
[7:3]
[2:1]
0
2
2
C Master Current Read Count Register
C Address 0 Register
Name
I2CADR
R/W
Name
I2CMADR
R/W
I2C0MCNT1, I2C1MCNT1
0xFFFF0814, 0xFFFF0914
0x00, 0x00
Read only
This 8-bit MMR holds the number of bytes
received so far during a read sequence with a
slave device.
I2C0ADR0, I2C1ADR0
0xFFFF0818, 0xFFFF0918
0x00
Read/write
This 8-bit MMR holds the 7-bit slave address +
the read/write bit when the master begins
communicating with a slave.
Description
These bits contain the 7-bit address of the
required slave device.
Bit 0 is the read/write bit.
When this bit = 1, a read sequence is
requested.
When this bit = 0, a write sequence is
requested.
Description
These bits must be set to [11110b] in 10-bit
address mode.
These bits contain ADDR[9:8] in 10-bit
addressing mode.
Read/write bit.
When this bit = 1, a read sequence is
requested.
When this bit = 0, a write sequence is
requested.
ADuC7124/ADuC7126