ADUC814BRU Analog Devices Inc, ADUC814BRU Datasheet
ADUC814BRU
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ADUC814BRU Summary of contents
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FEATURES ANALOG I/O 6-channel 247 kSPS ADC 12-bit resolution ADC high speed data capture mode Programmable reference via on-chip DAC for low level inputs, ADC performance specified to V Dual voltage output DACs 12-bit resolution, 15 µs settling time Memory ...
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ADuC814 TABLE OF CONTENTS Specifications..................................................................................... 4 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Description ............................ 10 Terminology .................................................................................... 12 ADC Specifications .................................................................... 12 DAC Specifications..................................................................... 12 Typical Performance Curves ......................................................... 13 ADuC814 Architecture, Main Features ....................................... ...
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Serial Peripheral Interface..........................................................44 MISO (Master In, Slave Out Data I/O Pin) .........................44 MOSI (Master Out, Slave In Pin)..........................................44 SCLOCK (Serial Clock I/O Pin) ...........................................44 SS (Slave Select Input Pin) .....................................................44 Using the SPI Interface...........................................................45 SPI Interface—Master Mode .................................................45 SPI Interface—Slave ...
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ADuC814 SPECIFICATIONS Table specifications unless otherwise specified MIN MAX Parameter ADC CHANNEL SPECIFICATIONS A GRADE 2,3 DC ...
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Parameter 9 TEMPERATURE MONITOR Voltage Output at 25ºC Voltage TC Accuracy Accuracy DAC CHANNEL SPECIFICATIONS 10 DC ACCURACY Resolution Relative Accuracy 11 Differential Nonlinearity Offset Error Gain Error Gain Error Mismatch ANALOG OUTPUTS Voltage Range_0 Voltage Range_1 Output Impedance I ...
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ADuC814 Parameter 14 SCLOCK and RESET Only (Schmitt-Triggered Inputs T– V – T– INPUT CURRENTS P1.2–P1.7, DLOAD 15 SCLOCK RESET 15 P1.0, P1.1, Port 3 (includes MISO, MOSI/SDATA and SS ) INPUT CAPACITANCE CRYSTAL OSCILLATOR ...
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Parameter 16 Oscillator Powered Down Wake-Up with INT0 Interrupt 2 Wake-Up with SPI/I C Interrupt Wake-Up with External RESET After External RESET in Normal Mode After WDT Reset in Normal Mode FLASH/EE MEMORY RELIABILITY 17 CHARACTERISTICS 18 Endurance Data Retention ...
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ADuC814 1 Temperature range –40ºC to +125ºC. 2 ADC linearity is guaranteed when operating in nonpipelined mode, i.e., ADC conversion followed sequentially by a read of the ADC result. ADC linearity is also guaranteed during normal MicroConverter core operation. 3 ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Temperature = 25°C, unless otherwise noted Parameter AV to AGND AGND AGND to DGND 2 Analog Input Voltage to AGND Reference Input Voltage to AGND ...
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ADuC814 PIN CONFIGURATION AND FUNCTION DESCRIPTION Table 3. Pin Descriptions Pin No. Mnemonic Type Function 1 DGND S Digital Ground. Ground reference point for the digital circuitry. 2 DLOAD I Debug/Serial Download Mode. Enables when pulled high through a resistor ...
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Pin No. Mnemonic Type Function Decoupling Input for On-Chip Reference. Connect 0.1 µF between this pin and AGND. REF 18–21 P1.4–P1.7 I Port 1.4 to P1.7. These pins have no digital output drivers, i.e., they can only ...
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ADuC814 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point1/2 LSB below ...
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... ADuC814 under various operating conditions. Note that all typical plots in this section were generated using the ADuC814BRU, i.e., the B-grade part. Figure 3 and Figure 4 show typical ADC integral nonlinearity (INL) errors from ADC Code 0 to Code 4095 and 3 V supplies, respectively ...
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ADuC814 0.30 0.25 0.20 0.15 0.10 0.05 0 –0.50 –0.10 –0. –0. 152kHz S –0.25 0 511 1023 1535 2047 2559 ADC CODES Figure 7. Typical DNL Error, V 0.30 AV /DV ...
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Figure 13 and Figure 14 show typical FFT plots for the ADuC814. These plots were generated using an external clock input via P3.5 to achieve coherent sampling. The ADC is using its internal reference (2.5 V) sampling a full-scale, 10 ...
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ADuC814 ADuC814 ARCHITECTURE, MAIN FEATURES The ADuC814 is a fully integrated 247 kSPS 12-bit data acquisition system incorporating a high performance multi- channel ADC, an 8-bit MCU, and program/data Flash/EE memory on a single chip. This low power device operates ...
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MEMORY ORGANIZATION The ADuC814 does not have Port 0 and Port 2 pins and therefore does not support external program or data memory interfaces. The device executes code from the internal 8-kByte Flash/EE program memory. This internal code space can ...
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ADuC814 The SFR space is mapped to the upper 128 bytes of internal data memory space and is accessed by direct addressing only. It provides an interface between the CPU and all on-chip periph- erals. A block diagram showing the ...
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Power Control SFR The power control (PCON) register contains bits for power-saving options and general-purpose status flags as shown in Table 5. SFR Address 87H Power-On Default 00H Bit Addressable No SMOD SERIPD INT0PD Table 5. PCON SFR Bit Designations ...
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ADuC814 SPECIAL FUNCTION REGISTERS All registers, except the program counter and the four general- purpose register banks, reside in the SFR area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and all ...
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ADC CIRCUIT INFORMATION GENERAL OVERVIEW The ADC block incorporates a 4.05 msec, 6-channel, 12-bit resolution, single-supply ADC. This block provides the user with a multichannel multiplexer, track-and-hold amplifier, on- chip reference, offset calibration features and ADC. All compo- nents in ...
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ADuC814 SFR INTERFACE TO ADC BLOCK The ADC operation is fully controlled via three SFRs: ADCCON1, ADCCON2, and ADCCON3. These three registers control the mode of operation. ADCCON1 (ADC CONTROL SFR 1) The ADCCON1 register controls conversion and acquisition times, ...
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ADCCON2 (ADC CONTROL SFR 2) The ADCCON2 (byte addressable) register controls ADC channel selection and conversion modes as detailed below. SFR Address D8H SFR Power-On Default 00H Bit Addressable Yes ADCI ADCSPI CCONV Table 7. ADCCON2 SFR Bit Designations Bit ...
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ADuC814 ADCCON3 (ADC CONTROL SFR 3) The ADCCON3 register controls the operation of various calibration modes as well as giving an indication of ADC busy status. SFR Address F5H SFR Power-On Default 00H BUSY GNCLD Table 8. ADCCON3 SFR Bit ...
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DRIVING THE ADC The ADC incorporates a successive approximation architecture (SAR) involving a charge-sampled input stage. Each ADC con- version is divided into two distinct phases as defined by the position of the switches in Figure 25. During the sampling ...
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ADuC814 Table 10. Some Single-Supply Op Amps Op Amp Model Characteristics OP281/OP481 Micropower OP191/OP291/OP491 I/O good OP196/OP296/OP496 I OP183/OP283 High gain-bandwidth product OP162/OP262/OP462 High GBP, micropackage AD820/OP822/OP824 FET input, low cost AD823 FET input, ...
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Both the ADCCLK frequency and the acquisition time are used in determining the ADC conversion time. Two other parameters are also used in this calculation. To convert the acquired signal into its corresponding digital output word takes 15 ADCCLK periods ...
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ADuC814 CONVST BUSY SCLOCK MOSI ADCDATAH In this mode, the ADC to SPI data transfer occurs during the next ADC conversion. To avoid loss of an ADC result, the user must ensure that the ADC to SPI transfer rate is ...
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ADC transfer function, effectively decreasing the slope of the transfer function. The maximum analog input signal range for which the gain coefficient can compensate is 1.035 ...
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ADuC814 NONVOLITILE FLASH/EE MEMORY FLASH/EE MEMORY OVERVIEW The ADuC814 incorporates Flash/EE memory technology on- chip to provide the user with nonvolatile, in-circuit reprogram- mable code and data memory space. Flash/EE memory takes the flexible in-circuit reprogrammable features of EEPROM and ...
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USING FLASH/EE PROGRAM MEMORY The Flash/EE program memory array can be programmed in one of two modes: serial downloading and parallel programming. Serial Downloading (In-Circuit Programming) As part of its factory boot code, the ADuC814 facilitates code download via the ...
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ADuC814 USING FLASH/EE DATA MEMORY The user Flash/EE data memory array consists of 640 bytes that are configured into 160 (00H to 9FH) 4-byte pages as shown in Figure 36. 9FH BYTE 1 BYTE 2 BYTE 3 BYTE 4 00H ...
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FLASH/EE MEMORY TIMING The typical program/erase times for the Flash/EE data memory are Erase Full Array (640 bytes Erase Single Page (4 bytes Program Page (4 bytes) 250 µs Read Page (4 bytes) Within single instruction ...
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ADuC814 USER INTERFACE TO OTHER ON-CHIP ADuC814 PERIPHERALS This section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DACS The ADuC814 incorporates ...
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DACxH/L DAC0 and DAC1 Data Registers Function DAC Data Registers, written by the user to update the DAC outputs. SFR Address DAC0L (DAC0 data low byte) –> F9H DAC0H (DAC0 data high byte) –> FAH; DAC1L (DAC1 data low byte) ...
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ADuC814 5 DAC LOADED WITH 0FFFH DAC LOADED WITH 0000H SOURCE/SINK CURRENT (mA) Figure 40. Source and Sink Current Capability with V 4 DAC LOADED WITH 0FFFH 3 1 DAC LOADED WITH 0000H ...
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ON-CHIP PLL The ADuC814 is intended for use with a 32.768 kHz watch crystal. An on-board PLL locks onto a multiple (512) of this 32.768kHz frequency to provide a stable 16.777216 MHz clock for the system. The core can operate ...
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ADuC814 TIME INTERVAL COUNTER (TIC) A time interval counter is provided on-chip for counting longer intervals than the standard 8051 compatible timers are capable of. The TIC is capable of time-out intervals ranging from 1/128th second to 255 hours. Furthermore, ...
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TIMECON TIC CONTROL REGISTER SFR Address A1H Power-On Default 00H Bit Addressable No --- TFH Table 14. TIMECON SFR Bit Designations Bit No. Name Description 7 --- Reserved. 6 TFH Twenty-Four Hour Select Bit. Set by the user to enable ...
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ADuC814 INTVAL User Time Interval Select Register Function User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is ...
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WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC814 enters an erroneous state, possibly due to a programming error, electrical noise, or RFI. The ...
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ADuC814 POWER SUPPLY MONITOR As its name suggests, the power supply monitor, once enabled, monitors the supply ( the ADuC814. It indicates when DD any of the supply pins drop below one of four user-selectable voltage trip points ...
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ADuC814 CONFIGURATION REGISTER (CFG814) The ADuC814 is housed in a 28-lead TSSOP package. To maintain as much functional compatibility with other MicroConverter products, some pins share multiple I/O functionality. Switching between these functions is controlled via the ADuC814 configuration SFR, ...
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ADuC814 SERIAL PERIPHERAL INTERFACE The ADuC814 integrates a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industry-standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. Note that ...
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Bit No. Name Description 1 2 CPHA Clock Phase Select Bit. Set by the user if the leading SCLOCK edge is to transmit data. Cleared by the user if the trailing SCLOCK edge is to transmit data. 1 SPR1 SPI ...
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ADuC814 COMPATIBLE INTERFACE The ADuC814 supports a 2-wire serial interface mode that compatible. The I C compatible interface shares its pins with the on-chip SPI interface, and therefore the user can enable ...
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COMPATIBLE ON-CHIP PERIPHERALS This section gives a brief overview of the various secondary peripheral circuits that are available to the user on-chip. These functions are fully 8051 compatible and are controlled via standard 8051 SFR bit definitions. Parallel I/O ...
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ADuC814 TIMERS/COUNTERS The ADuC814 has three 16-bit timer/counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware has been included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists ...
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TCON Timer/Counter 0 and 1 Control Register SFR Address 88H Power-On Default 00H Bit Addressable Yes TF1 TR1 These bits are not used in the control of Timer/Counter 0 and 1, but are used instead in the control and monitoring ...
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ADuC814 TIMER/COUNTER 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for both Timer 0 and Timer ...
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T2CON Timer/Counter 2 Control Register SFR Address C8H Power-On Default 00H Bit Addressable Yes TF2 EXF2 RCLK Table 24. T2CON SFR Bit Designations Bit No. Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 ...
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ADuC814 TIMER/COUNTER 2 OPERATING MODES This section describes the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table 27. Table 25. Mode Selection in T2CON RCLK (or) TCLK CAP2 ...
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UART SERIAL INTERFACE The serial port is full duplex, meaning it can transmit and receive simultaneously also receive-buffered, meaning it can begin receiving a second byte before a previously received byte has been read from the receive register. ...
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ADuC814 Mode 0: 8-Bit Shift Register Mode Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted ...
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Mode 2: 9-Bit UART with Fixed Baud Rate Mode 2 is selected by setting SM0 and clearing SM1. In this mode, the UART operates in 9-bit mode with a fixed baud rate. The baud rate is fixed at Core_Clk/64 by ...
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ADuC814 Timer 2 Generated Baud Rates Baud rates can also be generated using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted/received. Because Timer 2 ...
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INTERRUPT SYSTEM The ADuC814 provides a total of twelve interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs. IE Interrupt Enable Register IP Interrupt Priority Register IEIP2 Secondary ...
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ADuC814 IP Interrupt Priority Register SFR Address B8H Power-On Default 00H Bit Addressable Yes --- PADC Table 30. IP SFR Bit Designations Bit No. Name Description 7 --- Reserved. 6 PADC ADC Interrupt Priority. Written to by user to set ...
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Interrupt Priority The interrupt enable registers are written by the user to enable individual interrupt sources, while the interrupt priority registers allow the user to select one of two priority levels for each interrupt. An interrupt of a high priority ...
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ADuC814 ADuC814 HARDWARE DESIGN CONSIDERATIONS This section outlines some key hardware design considerations for integrating the ADuC814 into any hardware system. CLOCK OSCILLATOR As described earlier, the core clock frequency for the ADuC814 is generated from an on-chip PLL that ...
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Power-Saving Modes Setting the idle and power-down mode bits, PCON.0 and PCON.1, respectively, in the PCON SFR described in Table 5, allows the chip to be switched from normal mode to idle mode, and also to full power-down mode. In ...
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ADuC814 PLACE ANALOG a. COMPONENTS HERE AGND PLACE ANALOG b. COMPONENTS HERE AGND PLACE ANALOG c. COMPONENTS HERE GND Figure 58. System Grounding Schemes In all of these scenarios, and in more complicated real-life appli- cations, keep in mind the ...
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HEADER FOR EMULATION ACCESS (NORMALLY OPEN) DOWN LOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) ANALOG INPUT Single-Pin Emulation Mode Also built into the ADuC814 is a dedicated controller for single- pin in-circuit emulation (ICE) using standard production ADuC814 devices. In this ...
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ADuC814 TIMING SPECIFICATIONS Table 34. Clock Input (External Clock Driven XTAL1 Parameter t XTAL1 Period CK t XTAL1 Width Low CKL t XTAL1 Width High ...
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Table 35. UART Timing (Shift Register Mode) Parameter t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock QVXH t Input Data Setup to Clock DVXH t Input Data Hold after Clock XHDX t Output Data Hold ...
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ADuC814 Table 36. SPI Master Mode Timing (CPHA = 1) Parameter t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU ...
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Table 37. SPI Master Mode Timing (CPHA = 0) Parameter t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Output Setup before SCLOCK Edge DOSU t Data ...
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ADuC814 Table 38. SPI Slave Mode Timing (CPHA = 1) Parameter SCLOCK Edge SS t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Input ...
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Table 39. SPI Slave Mode Timing (CPHA = 0) Parameter SCLOCK Edge SS t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup ...
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ADuC814 OUTLINE DIMENSIONS PIN 1 0.15 0.05 COPLANARITY 9.80 9.70 9. 4.50 4.40 4. 0.65 BSC 1.20 MAX 0.30 0.20 0.19 SEATING 0.09 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 67. 28-Lead ...
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... ADuC814ARU-REEL −40°C to +125°C ADuC814ARU-REEL7 −40°C to +125°C ADuC814BRU −40°C to +125°C ADuC814BRU-REEL −40°C to +125°C ADuC814BRU-REEL7 −40°C to +125°C QuickStart Development System Model EVAL-ADUC814QS 1 EVAL-ADUC814QSP 1 Only available to order through the web. Package Description ...
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ADuC814 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips Patent Rights to use these components ...