ADUC847BCP8-3 Analog Devices Inc, ADUC847BCP8-3 Datasheet - Page 99
![IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC](/photos/6/62/66273/505-56-csp_sml.jpg)
ADUC847BCP8-3
Manufacturer Part Number
ADUC847BCP8-3
Description
IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet
1.EVAL-ADUC845QSZ.pdf
(108 pages)
Specifications of ADUC847BCP8-3
Core Processor
8052
Core Size
8-Bit
Speed
12.58MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PSM, PWM, Temp Sensor, WDT
Number Of I /o
34
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 10x24b; D/A 1x12b, 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
56-LFCSP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
EVAL-ADUC847QSZ - KIT DEV QUICK START FOR ADUC847
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 99 of 108
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Table 68. SPI MASTER MODE TIMING (CPHA = 1) Parameter
t
t
t
t
t
t
t
t
t
____________________________________________
1
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, that is, core clock frequency = 1.57 MHz.
b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
SCLOCK Low Pulse Width
SCLOCK High Pulse Width
Data Output Valid After SCLOCK Edge
Data Input Setup Time Before SCLOCK Edge
Data Input Hold Time After SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
(CPOL = 0)
(CPOL = 1)
SCLOCK
SCLOCK
MOSI
MISO
1
1
t
DAV
t
SH
t
DSU
Figure 76. SPI Master Mode Timing (CHPA = 1)
MSB IN
t
MSB
DHD
t
SL
Rev. B | Page 99 of 108
t
DF
t
DR
BITS 6–1
BITS 6–1
t
SR
Min
100
100
ADuC845/ADuC847/ADuC848
t
LSB IN
SF
LSB
Typ
635
635
10
10
10
10
Max
50
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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