ADUM1234BRWZ-RL Analog Devices Inc, ADUM1234BRWZ-RL Datasheet - Page 3

• Manufacturer Part Number: ADUM1234BRWZ-RL
• Description: IC,Dual MOSFET Driver,SOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: iCoupler®r

Specifications of ADUM1234BRWZ-RL

• Inputs - Side 1/side 2: 2/0
• Number Of Channels: 2
• Isolation Rating: 2500Vrms
• Voltage - Supply: 4.5 V ~ 5.5 V
• Data Rate: 10Mbps
• Propagation Delay: 124ns
• Output Type: Logic
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
4.5 V ≤ V
operating range, unless otherwise noted. All typical specifications are at T
relative to their respective grounds.
Table 1.
Parameter
DC SPECIFICATIONS
SWITCHING SPECIFICATIONS
1
2
3
4
5
6
7
8
Short-circuit duration less than 1 second.
The minimum pulse width is the shortest pulse width at which the specified timing parameters are guaranteed.
The maximum switching frequency is the maximum signal frequency at which the specified timing parameters are guaranteed.
t
measured from the 50% level of the rising edge of the V
Channel-to-channel matching, rising or falling edges, is the magnitude of the propagation delay diffe
are either both rising or falling edges. The supply voltages and the loads on each channel are equal.
Channel-to-channel matching, rising vs. falling edges, is the magnitude of the propagation delay difference between two channels of the same part when one input is
a rising edge and the other input is a falling edge. The supply voltages and loads on each channel are equal.
Part-to-part matching, rising or falling edges, is the magnitude of the propagation delay difference between the same channels of two different parts when the inputs
are either both rising or falling edges. The supply voltages, temperatures, and loads of each part are equal.
Part-to-part matching, rising vs. falling edges, is the magnitude of the propagation delay difference between the same cha
is
PHL
Minimum Pulse Width
Maximum Switching Frequency
Propagation Delay
Pulse Width Distortion, |t
Channel-to-Channel Matching,
Channel-to-Channel Matching,
Part-to-Part Matching, Rising or Falling Edges
Part-to-Part Matching, Rising vs. Falling
Output Rise/Fall Time (10% to 90%)
Input Supply Current, Quiescent
Output Supply Current A or Output Supply
Input Supply Current, 10 Mbps
Output Supply Current A or Output Supply
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Output Short-Circuit Pulsed Current
a rising edge and the other input is a falling edge. The supply voltages, temperatures, and loads of each part are equal.
propagation delay is measured from the 50% level of the falling edge of the V
Change vs. Temperature
Rising or Falling Edges
Rising vs. Falling Edges
Edges
Current B, Quiescent
Current B, 10 Mbps
DD1
8
≤ 5.5 V, 12 V ≤ V
4
2
PLH
5
6
− t
DDA
PHL
3
≤ 18 V, 12 V ≤ V
|
1
Ix
7
signal to the 50% level of the rising edge of the V
DDB
Symbol
I
I
I
I
I
I
I
I
V
V
V
I
PW
t
PWD
t
V
DDI(Q)
DDA(Q)
DDB(Q)
DDI(10)
DDA(10)
DDB(10)
IA
DISABLE
OA(SC)
PHL
R
IH
IL
OAH
OAL
/t
, I
≤ 18 V. All minimum/maximum specifications apply over the entire recommended
, t
F
IB
,V
,V
,
, I
PLH
,
,
OBL
OBH
OB(SC)
Rev. 0 | Page 3 of 12
Min
−10
0.7 × V
V
V
100
10
97
DDA
DDB
Ix
signal to the 50% level of the falling edge of the V
− 0.1,
− 0.1
DD1
A
= 25°C, V
Typ
3.0
0.3
6.0
16
+0.01
V
124
100
DDA
, V
rence between two channels of the same part when the inputs
DDB
DD1
Ox
= 5 V, V
signal.
Max
4.2
1.2
9.0
22
+10
0.3 × V
0.1
100
160
8
5
13
55
63
25
DDA
DD1
= 15 V, V
nnels of two different parts when one input
Unit
mA
mA
mA
mA
μA
V
V
V
V
mA
ns
Mbps
ns
ps/°C
ns
ns
ns
ns
ns
ns
DDB
Ox
Test Conditions
C
0 V ≤ V
I
I
C
C
C
C
C
C
C
C
C
C
signal. t
OA
OA
L
L
L
L
L
L
L
L
L
L
L
= 15 V. All voltages are
= 200 pF
, I
, I
= 200 pF
= 200 pF
= 200 pF
= 200 pF
= 200 pF
= 200 pF
= 200 pF
= 200 pF, Input t
= 200 pF, Input t
= 200 pF
OB
OB
IA
= −1 mA
= +1 mA
PLH
, V
propagation delay is
ADuM1234
IB
, V
DISABLE
R
R
≤ V
= 3 ns
= 3 ns
DD1