ADUM2210TRWZ-RL Analog Devices Inc, ADUM2210TRWZ-RL Datasheet - Page 6
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ADUM2210TRWZ-RL
Manufacturer Part Number
ADUM2210TRWZ-RL
Description
5kV DUAL-CHANNEL DIGITAL ISOLATORS
Manufacturer
Analog Devices Inc
Series
iCoupler®r
Datasheet
1.ADUM2210SRWZ.pdf
(20 pages)
Specifications of ADUM2210TRWZ-RL
Operating Temperature
-40°C ~ 125°C
Inputs - Side 1/side 2
2/0
Number Of Channels
2
Isolation Rating
5000Vrms
Voltage - Supply
3 V ~ 5.5 V
Data Rate
10Mbps
Propagation Delay
50ns
Output Type
Logic
Package / Case
16-SOIC (0.300", 7.50mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADuM2210/ADuM2211
Parameter
1
2
3
4
5
6
7
8
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Figure 6
for total I
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
t
measured from the 50% level of the rising edge of the V
t
load within the recommended operating conditions.
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
CM
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See
information on per-channel supply current for unloaded and loaded conditions. See the
current for a given data rate.
PHL
PSK
ADuM221xTR
For All Models
H
propagation delay is measured from the 50% level of the falling edge of the V
is the magnitude of the worst-case difference in t
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching,
Channel-to-Channel Matching,
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
Common-Mode Transient Immunity
Refresh Rate
Input Dynamic Supply Current, per Channel
Output Dynamic Supply Current, per
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
Codirectional Channels
Opposing Directional Channels
at Logic High Output
at Logic Low Output
Channel
Change vs. Temperature
through
DD1
and I
8
DD2
Figure 8
supply currents as a function of data rate for ADuM2210 and ADuM2211 channel configurations.
for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See
4
3
2
7
7
5
PLH
6
−t
PHL
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
|
4
6
PHL
8
and/or t
Ix
signal to the 50% level of the rising edge of the V
Symbol
PW
t
PWD
t
t
t
t
|CM
|CM
f
I
I
DDI (D)
DDO (D)
r
PHL
PSK
PSKCD
PSKOD
R
/t
, t
F
PLH
H
L
|
|
PLH
that is measured between units at the same operating temperature, supply voltages, and output
Rev. 0 | Page 6 of 20
Min
10
20
25
25
Ix
signal to the 50% level of the falling edge of the V
Power Consumption
Typ
5
3.0
35
35
1.1
0.10
0.03
O
> 0.8 V
Max
100
60
3
22
3
22
DD2
Ox
. CM
signal.
section for guidance on calculating per-channel supply
L
is the maximum common-mode voltage slew rate
Unit
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
ns
kV/μs
kV/μs
Mbps
mA/Mbps
mA/Mbps
Figure 6
Power Consumption
Test Conditions
C
C
C
C
C
C
C
C
C
V
transient magnitude = 800 V
V
transient magnitude = 800 V
L
L
L
L
L
L
L
L
L
Ix
Ix
Ox
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= V
= 0 V, V
signal. t
through
DD1
Figure 9
or V
CM
PLH
Figure 8
= 1000 V,
DD2
propagation delay is
through
, V
CM
section. See
for
= 1000 V,
Figure 11