ADV3228ACPZ Analog Devices Inc, ADV3228ACPZ Datasheet
ADV3228ACPZ
Specifications of ADV3228ACPZ
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ADV3228ACPZ Summary of contents
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FEATURES 8 × 8 high speed, nonblocking switch array Pinout and functionally equivalent to the Drop-in compatible with ADV3224/ADV3225 Complete solution Buffered inputs Programmable high impedance outputs 8 output amplifiers (ADV3228 (ADV3229) Drives 150 ...
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ADV3228/ADV3229 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics (Serial) .................................................. 5 Logic Levels ................................................................................... 5 Timing Characteristics (Parallel) ............................................... 6 ...
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SPECIFICATIONS V = ± 25° 150 Ω, unless otherwise noted Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Gain Flatness Propagation Delay Settling Time Slew Rate NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential ...
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ADV3228/ADV3229 Parameter POWER SUPPLIES Supply Current Supply Voltage Range PSRR OPERATING TEMPERATURE RANGE Temperature Range θ JA Test Conditions/Comments Min AVCC, outputs enabled, no load AVCC, outputs disabled AVEE, outputs enabled, no load AVEE, outputs disabled DVCC, outputs enabled, no ...
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TIMING CHARACTERISTICS (SERIAL) Table 2. Parameter Serial Data Setup Time CLK Pulse Width Serial Data Hold Time CLK Pulse Separation, Serial Mode CLK to UPDATE Delay UPDATE Pulse Width CLK to DATAOUT Valid, Serial Mode Propagation Delay, UPDATE to Switch ...
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ADV3228/ADV3229 TIMING CHARACTERISTICS (PARALLEL) Table 4. Parameter Parallel Data Setup Time Address Setup Time CLK Pulse Width Parallel Data Hold Time Address Hold Time CLK Pulse Separation UPDATE Pulse Width CLK, UPDATE Rise and Fall Times RESET Time Timing Diagram—Parallel ...
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ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Supply Voltage (AVCC to AVEE) Digital Supply Voltage (DVCC to DGND) Supply Potential Difference (AVCC to DVCC) Ground Potential Difference (AGND to DGND) Maximum Potential Difference (DVCC to AVEE) Analog Input Voltage Digital ...
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ADV3228/ADV3229 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVCC AVEE AVCC AVEE AVCC AVEE AVCC AVEE AGND AVEE NOTES CONNECT. DO NOT CONNECT TO THIS PIN. 2. EXPOSED PADDLE. THE EXPOSED METAL PADDLE ON THE BOTTOM OF Table ...
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Pin No Mnemonic Description D3, D2, D1, D0 Parallel Data Input. A2, A1, A0 Parallel Output Address Input. SER/PAR Serial/Parallel Mode Select (Control Pin). Second Rank Write ...
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ADV3228/ADV3229 TRUTH TABLE AND LOGIC DIAGRAM 1 Table 8. Operation Truth Table CE UPDATE CLK DATAIN DATAOUT Data Data D0…D3 Not applicable in parallel mode ...
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TYPICAL PERFORMANCE CHARACTERISTICS 4 OUTPUT SIGNAL, UNICAST 3 OUTPUT SIGNAL, BROADCAST –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 – 200mV p-p OUT – 100 FREQUENCY (MHz) Figure 7. ADV3228 Small ...
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ADV3228/ADV3229 4 3 10.4pF –1 1.2pF –2 –3 0pF –4 –5 –6 –7 –8 – p-p OUT – 100 FREQUENCY (MHz) Figure 13. ADV3228 Large Signal Frequency Response with Capacitive Loads 0.15 ...
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RISING EDGE PULSE RISING EDGE SLEW RATE 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 TIME (ns) Figure 19. ADV3228 Rising Edge Slew Rate 2.0 1.5 1.0 0.5 0 –0.5 –1.0 ...
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ADV3228/ADV3229 –10 –20 –30 –40 –50 –60 –70 –80 –90 0 FREQUENCY (MHz) Figure 25. ADV3228 Power Supply Rejection 400 350 300 250 200 150 100 100 1000 FREQUENCY ...
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IN11-OUT3: VICTIM CHANNEL IN12-OUT4: AGGRESSOR – p-p OUT –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 1 10 100 FREQUENCY (MHz) Figure 31. ADV3228 Crosstalk, One Adjacent Channel, RTO 0 IN3-OUT3: VICTIM CHANNEL V ...
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ADV3228/ADV3229 1M 100k 10k 1k 100 FREQUENCY (MHz) Figure 37. ADV3228 Output Impedance, Disabled 100 10 1 0.1 0 FREQUENCY (MHz) Figure 38. ADV3228 Output Impedance, Enabled 2.0 UPDATE 1.5 V 1.0 0.5 ...
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UPDATE 0.0375 0.0250 0.0125 V 0 –0.0125 –0.0250 –0.0375 –0.0500 –15 –10 – TIME (ns) Figure 43. ADV3228 Switching Glitch 4 UPDATE OUT 0 V OUT –20 ...
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ADV3228/ADV3229 0.001 0 –0.001 –0.002 –0.003 –0.004 –0.005 –0.006 –0.007 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 INPUT VOLTAGE (V) Figure 49. ADV3228 Differential Phase Error 8.5V ...
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REF: 50Ω 100Ω L TONE SPACING: 1MHz 10 10 100 INPUT FREQUENCY (MHz) Figure 55. ADV3229 Second-Order Intercept, 100 Ω Load ...
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ADV3228/ADV3229 CIRCUIT DIAGRAMS INx 1.8pF Figure 58. Analog Input Figure 59. Analog Output Enabled AVCC DVCC INx, OUTx AGND AGND DGND Figure 60. ESD Map A[2:0], CE, CLK, 1kΩ D[4:0], DATAIN, SER/PAR, UPDATE Figure 61. Logic Input OUTx CLK, RESET, ...
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THEORY OF OPERATION The ADV3228 (G = +1) and ADV3229 (G = +2) are crosspoint arrays with eight outputs, each of which can be connected to any one of eight inputs. Organized by output row, eight switchable input transconductance stages ...
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ADV3228/ADV3229 APPLICATIONS INFORMATION The ADV3228/ADV3229 have two options for changing the programming of the crosspoint matrix. In the first option, a serial word of 40 bits can be provided, which updates the entire matrix each time the 40-bit word is ...
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In parallel mode, the CLK pin is level sensitive, whereas in serial mode edge triggered. POWER-ON RESET When powering up the ADV3228/ADV3229 usually desirable to have the outputs come up in the disabled ...
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... SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADV3228ACPZ −40°C to +85°C ADV3228-EVALZ ADV3229ACPZ −40°C to +85°C ADV3229-EVALZ RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...