ADV7180KCP32Z Analog Devices Inc, ADV7180KCP32Z Datasheet - Page 12
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ADV7180KCP32Z
Manufacturer Part Number
ADV7180KCP32Z
Description
10-bit 4x Oversampling SDTV Decoder
Manufacturer
Analog Devices Inc
Type
Video Decoderr
Datasheet
1.ADV7180BSTZ.pdf
(116 pages)
Specifications of ADV7180KCP32Z
Design Resources
Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
Applications
Digital Cameras, Mobile Phones, Portable Video
Voltage - Supply, Analog
1.71 V ~ 1.89 V
Voltage - Supply, Digital
1.65 V ~ 2 V
Mounting Type
Surface Mount
Package / Case
32-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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ADV7180
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
32-LEAD LFCSP
Table 9. 32-Lead LFCSP Pin Function Descriptions
Pin No.
1
2, 29
3
4
5 to 10, 15, 16
11
12
13
14, 30
17
18
19, 23, 24
20
21
22
25
26
27
28
31
32
Mnemonic
HS
DGND
DVDDIO
SFL
P7 to P2, P1, P0
LLC
XTAL1
XTAL
DVDD
ELPF
PVDD
A
VREFP
VREFN
AVDD
RESET
ALSB
SDATA
SCLK
VS/FIELD
INTRQ
EPAD (EP)
IN
1 to A
IN
3
Type
O
G
P
O
O
O
O
I
P
I
P
I
O
O
P
I
I
I/O
I
O
O
Description
Horizontal Synchronization Output Signal.
Ground for Digital Supply.
Digital I/O Supply Voltage (1.8 V to 3.3 V).
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.
Video Pixel Output Port.
Line-Locked Output Clock for the Output Pixel Data. Nominally 27 MHz but varies up or
down according to video line length.
This pin should be connected to the 28.6363 MHz crystal or not connected if an external
1.8 V,28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the
crystal must be a fundamental crystal.
Input Pin for the 28.6363 MHz Crystal. This pin can be overdriven by an external 1.8 V,
28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
Digital Supply Voltage (1.8 V).
The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 59.
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
Internal Voltage Reference Output. See Figure 59 for recommended output circuitry.
Internal Voltage Reference Output. See Figure 59 for recommended output circuitry.
Analog Supply Voltage (1.8 V).
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7180 circuitry.
This pin selects the I
for a write is 0x40; for ALSB set to Logic 1, the address selected is 0x42.
I
I
Vertical Synchronization Output Signal/Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video
(see Table 108).
The exposed pad must be connected to GND.
DVDDIO
NOTES
1. THE EXPOSEDPAD MUST BE CONNECTEDTO GND.
2
2
C Port Serial Data Input/Output Pin.
C Port Serial Clock Input. The maximum clock rate is 400 kHz.
DGND
SFL
HS
P7
P6
P5
Figure 8. 32-Lead LFCSP Pin Configuration
1
2
3
4
5
6
7
Rev. F | Page 12 of 116
PIN1
INDICATOR
(Not to Scale)
ADV7180
TOP VIEW
2
C address for the ADV7180. For ALSB set to Logic 0, the address selected
LFCSP
24
23
22
21
20
19
18
17
A
A
AVDD
VREFN
VREFP
A
PVDD
ELPF
IN
IN
IN
3
2
1