ADV7393-DBRDZ Analog Devices Inc, ADV7393-DBRDZ Datasheet - Page 43

• Manufacturer Part Number: ADV7393-DBRDZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of ADV7393-DBRDZ

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Main Purpose: Video, Video Encoder
• Utilized Ic / Part: ADV7393
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SR7 to
SR0
0xBB
1
2
Table 33. Register 0xC9 to Register 0xCE
SR7 to
SR0
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
1
x = Logic 0 or Logic 1.
See the HD Interlace External HSYNC and VSYNC Considerations section for information about the first encoder version.
The use of P0 as the teletext input pin is available on the ADV7392/ADV7393 (40-pin devices) only.
Register
Field count
Register
Teletext control
Teletext request
control
TTX Line Enable 0
TTX Line Enable 1
TTX Line Enable 2
TTX Line Enable 3
Bit Description
Teletext enable
Teletext request mode
Teletext input pin
select
Reserved
Teletext request falling
edge position control
Teletext request rising
edge position control
Teletext on odd fields
Teletext on odd fields
Teletext on even fields
Teletext on even fields
Bit Description
Field count
Reserved
Encoder version code
1
7
0
0
0
…
1
1
22
14
22
14
Rev. B | Page 43 of 108
6
0
0
0
…
1
1
21
13
21
13
5
0
0
0
…
1
1
20
12
20
12
7
0
0
Bit Number
4
0
0
1
…
0
1
19
11
19
11
6
0
1
ADV7390/ADV7391/ADV7392/ADV7393
5
0
3
0
0
0
…
1
1
18
10
18
10
Bit Number
4
0
2
0
1
0
0
…
1
1
17
9
17
9
3
0
1
0
1
0
0
…
1
1
16
8
16
8
1
2
x
0
0
1
0
1
…
0
1
15
7
15
7
1
x
Register Setting
Disabled.
Enabled.
Line request signal.
Bit request signal.
VSYNC.
P0.
Reserved.
0 clock cycles.
One clock cycle.
…
14 clock cycles.
15 clock cycles.
0 clock cycles.
One clock cycle.
…
14 clock cycles.
15 clock cycles.
Setting any of these bits
to 1 enables teletext on
the line number indicated
by the bit settings.
0
x
Register Setting
Read only
Reserved
Read only; first
encoder version
Read only; second
encoder version
2
Reset
Value
0x00
0x00
0x00
0x00
0x00
0x00
Reset
Value
0x0X