AMP02FSZ-RL Analog Devices Inc, AMP02FSZ-RL Datasheet - Page 4

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AMP02FSZ-RL

Manufacturer Part Number
AMP02FSZ-RL
Description
SOL-16 WITH TAPE & REEL
Manufacturer
Analog Devices Inc
Type
Instrumentation Ampr
Datasheet

Specifications of AMP02FSZ-RL

Amplifier Type
Instrumentation
Number Of Circuits
1
Slew Rate
6 V/µs
-3db Bandwidth
1.2MHz
Current - Input Bias
4nA
Voltage - Input Offset
40µV
Current - Supply
5mA
Current - Output / Channel
32mA
Voltage - Supply, Single/dual (±)
±4.5 V ~ 18 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
Number Of Channels
1
Number Of Elements
1
Power Supply Requirement
Dual
Common Mode Rejection Ratio
75dB
Voltage Gain Db
80dB
Input Resistance
16500@±15VMohm
Input Offset Voltage
0.2@±15VmV
Input Bias Current
0.02@±15VnA
Single Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (typ)
±5/±9/±12/±15V
Power Supply Rejection Ratio
75dB
Rail/rail I/o Type
No
Single Supply Voltage (min)
Not RequiredV
Single Supply Voltage (max)
Not RequiredV
Dual Supply Voltage (min)
±4.5V
Dual Supply Voltage (max)
±18V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
16
Package Type
SOIC W
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output Type
-
Gain Bandwidth Product
-
Lead Free Status / Rohs Status
Compliant
AMP02
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AMP02 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
Parameter
Input Offset Voltage
Output Offset Voltage
Power Supply
Rejection
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode
Rejection
Gain Equation Accuracy
Output Voltage Swing
Supply Current
*Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
WAFER TEST LIMITS*
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
(@ V
1
Symbol
V
V
PSR
I
I
IVR
CMR
V
I
DIE SIZE 0.103 inch
8
B
OS
SY
S
NOTE: PINS 1 and 8 are KELVIN CONNECTED
IOS
OOS
OUT
=
(2.62 mm
15 V, V
CM
2.95 mm, 7.73 sq. mm)
= 0 V, T
0.116 inch, 11,948 sq. mils
G = 10
Guaranteed by CMR Tests
G = 100
G = 10
Conditions
V
G = 1000
G = 100
G = 1
V
G = 1000
G = 1
R
G =
Die Characteristics
S
CM
L
= ± 4.8 V to ± 18 V
= 1 kΩ
50 kΩ
A
= ± 11 V
R
= 25 C, unless otherwise noted.)
G
–4–
+ 1, G = 1000
1. RG
2. –IN
3. +IN
4. V–
5. REFERENCE
6. OUT
7. V+
8. RG
9. SENSE
CONNECT SUBSTRATE TO V–
1
2
AMP02 GBC
200
8
110
110
95
75
20
10
± 11
110
110
95
75
0.7
± 12
6
Limits
Unit
µV max
mV max
dB
nA max
nA max
V min
dB
% max
V min
mA max
REV. E

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