CS4244-CNZ Cirrus Logic Inc, CS4244-CNZ Datasheet - Page 23

• Manufacturer Part Number: CS4244-CNZ
• Description: IC 4 Input / 5 Output CODEC
• Manufacturer: Cirrus Logic Inc

DS900PP2
4.2.2
Note:
4.2.3
Power-down
To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turn-
ing off the power. In order to do this in a controlled manner, it is recommended that all the converters be
muted to start the sequence. Next, set PDNx for all converters to 1 to power them down internally. Then,
FS/LRCK and SCLK can be removed if desired. Finally, the
must be set to ‘1’ for a period of 50 ms before applying reset or removing power or MCLK. During this
time, voltage on VQ and the audio outputs discharge gradually to GND. If power is removed before this
50 ms time period has passed, a transient will occur and a slight click or pop may be heard. There is no
minimum time for a power cycle. Power may be re-applied at any time.
It is important to note that all clocks should be applied and removed in the order specified in
MCLK is removed or applied before
result. If either SCLK or FS/LRCK is removed or applied before all PDNx bits are set to “1”, audible pops,
clicks and/or distortion can result.
Timings are approximate and based upon the nominal value of the passive components specified in the
“Typical Connection Diagram” on page
DAC DC Loading
Figure 10
to prevent pops and clicks. Thus any DC loads (RL
es are closed. These DC loads will pull the VQ voltage down towards ground. If the parallel combination
of all DC loads exceeds the specification shown in the Analog Output Characteristics tables on pages
shows the analog output configuration during power-up, with the AOUTx± pins clamped to VQ
Figure 9. System Level Initialization and Power-Up/Down Sequence
2 ms + (3000/ MCLK)
Write all required configuration
Start SCLK, FS/LRCK, SDINx
Clear PDN DACx & ADCx bits
Write VA_SEL bit (in 0Fh)
Apply VL, VA, and MCLK
settings to Control Port
Clear Mute ADCx bits
Clear Mute DACx bits
appropriately for VA
Set RST
delay dependent
unmute behavior
on DAC mute /
250 ms
(3000 /MCLK)
250 ms
2 ms +
RST
7. See
has been pulled low, audible pops, clicks and/or distortion can
Captured & Control
Operational
Unpowered
(>90% of Typical)
VCM Ready
Available on
Operational
System
System
I
DACx Fully
Port Ready
2
ADC Data
C Address
SDOUTx
Section 4.6.5.2
x
) on the output pins will be in parallel when the switch-
“VQ RAMP” bit in the "DAC Control 4" register
for volume ramp behavior.
Stop SCLK, FS/LRCK, SDINx
delay dependent
unmute behavior
Set all PDN DAC & ADC bits
Remove VL, VA, and MCLK
on DAC mute /
Set Mute ADCx bits
Set Mute DACx bits
Set VQ_RAMP bit
50 ms
Clear RST
CS4244
Figure
9. If
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