CS42L51-CNZR Cirrus Logic Inc, CS42L51-CNZR Datasheet - Page 39

• Manufacturer Part Number: CS42L51-CNZR
• Description: IC LV Stereo Codec F/Digital Audio Apps
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-CNZR

• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q3956082

DS679A2
4.5.4
4.6
LRCK
SCLK
SDOUT
SDIN
SDOUT
LRCK
SCLK
SDIN
LRCK
SCLK
SDIN
Digital Interface Formats
The serial port operates in standard I²S, Left-Justified or Right-Justified(DAC only) digital interface formats
with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the DAC on the rising edge of
SCLK.
rial Port” on page 20
Hardware
Quarter- and Half-Speed Mode
Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a
relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow
lower frequency sample rates; however, the DAC's noise floor, that normally rises out-of-band, will scale
with the lower sample rate and begin to rise within the audio band. QSM and HSM corrects for most of
this scaling, effectively increasing the dynamic range of the CODEC at lower sample rates, relative to
SSM.
Software
Control:
Control:
M S B
Figures 20-22
M S B
“Interface Control (Address 04h)” on page
“I²S/LJ” pin 3
AOUTA / AINxA
AOUTA / AINxA
L eft C h a n n el
AOUTA
L eft C h a n n el
for exact timing relationship between clocks and data.
L eft C h a n n el
Pin
illustrate the general structure of each format. Refer to
M S B
Figure 22. Right-Justified Format (DAC only)
Figure 21. Left-Justified Format
LO
HI
Figure 20. I²S Format
Setting
L S B
L S B
L S B
M S B
Left-Justified Interface
I²S Interface
49.
M S B
AOUTB / AINxB
AOUTB / AINxB
R ig ht C h a n n el
R ig ht C h a n n el
R ig ht C h a n n el
AOUTB
M S B
Selection
“Switching Specifications - Se-
L S B
L S B
CS42L51
MSB
L S B
MSB
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