CS42L52-DNZ Cirrus Logic Inc, CS42L52-DNZ Datasheet - Page 46

• Manufacturer Part Number: CS42L52-DNZ
• Description: IC,Soundcard Circuits,LLCC,40PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L52-DNZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 99 / 98
• Voltage - Supply, Analog: 1.65 V ~ 2.63 V
• Voltage - Supply, Digital: 1.65 V ~ 2.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1580 - REFERENCE DESIGN FOR CS42L52598-1508 - BOARD EVAL FOR 42LDB1 CODEC598-1505 - BOARD EVAL FOR CS42L52 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

46
6.5.6
6.6
6.6.1
6.6.2
6.6.3
6.6.4
M/S
7
Interface Control 1 (Address 06h)
MCLK Divide By 2
Divides the input MCLK by 2 prior to all internal circuitry.
Note:
Master/Slave Mode
Configures the serial port I/O clocking.
SCLK Polarity
Configures the polarity of the SCLK signal.
ADC Interface Format
Configures the digital interface format for data on SDOUT.
DSP Mode
Configures a data-packed interface format for both the ADC and DAC.
Notes:
1. Select the audio word length using the AWL[1:0] bits
2. The interface format for both the ADC and the DAC must be set to “Left-Justified” when DSP Mode
MCLKDIV2
0
1
Application:
M/S
0
1
INV_SCLK
0
1
ADCDIF
0
1
Application:
DSP
0
1
Application:
is enabled.
INV_SCLK
In slave mode, this bit is ignored when the AUTO bit
6
MCLK signal into CODEC
No divide
Divided by 2
“Serial Port Clocking” on page 34
Serial Port Clocks
Slave (input ONLY)
Master (output ONLY)
SCLK Polarity
Not Inverted
Inverted
ADC Interface Format
Left Justified
I²S
“Digital Interface Formats” on page 36
DSP Mode
Disabled
Enabled
“DSP Mode” on page 36
ADCDIF
5
DSP
4
5/13/08
DACDIF1
3
(“Audio Word Length” on page
(“Auto-Detect” on page
DACDIF0
2
AWL1
1
44) is disabled.
47).
CS42L52
AWL0
DS680F1
0