CS5341-DZZR Cirrus Logic Inc, CS5341-DZZR Datasheet - Page 15

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CS5341-DZZR

Manufacturer Part Number
CS5341-DZZR
Description
IC,A/D CONVERTER,DUAL,24-BIT,TSSOP,16PIN
Manufacturer
Cirrus Logic Inc
Datasheets
DS564F1
4. APPLICATIONS
4.1
4.2
* Quad-Speed Mode, 64x only available in Master Mode.
Single-, Double-, and Quad-Speed Modes
The CS5341 can support output sample rates from 2 kHz to 200 kHz. The proper speed mode can be de-
termined by the desired output sample rate and the external MCLK/LRCK ratio, as shown in
Operation as Either a Clock Master or Slave
The CS5341 supports operation as either a clock master or slave. As a clock master, the LRCK and SCLK
pins are outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the
LRCK and SCLK pins are inputs and require the left/right and serial clocks to be externally generated. The
selection of clock master or slave is made via the Mode pins as shown in
Double-Speed Mode
Single-Speed Mode
Quad-Speed Mode
Speed Mode
Table 1. Speed Modes and the Associated Output Sample Rates (Fs)
M1 (Pin 16)
0
0
1
1
M0 (Pin 1)
Table 2. CS5341 Mode Control
0
1
0
1
MCLK/LRCK
Ratio
512x
256x
256x
128x
128x
64x*
Clock Master, Single-Speed Mode
Clock Master, Double-Speed Mode
Clock Master, Quad-Speed Mode
Clock Slave, All Speed Modes
MODE
Output Sample Rate Range (kHz)
Table
172 - 200
100 - 200
86 - 100
50 - 100
43 - 50
2 - 50
2.
Table
CS5341
1.
15

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