CS5341-DZZR Cirrus Logic Inc, CS5341-DZZR Datasheet - Page 16

• Manufacturer Part Number: CS5341-DZZR
• Description: IC,A/D CONVERTER,DUAL,24-BIT,TSSOP,16PIN
• Manufacturer: Cirrus Logic Inc

16
4.2.1
4.2.2
MCLK
Operation as a Clock Master
As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally de-
rived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as
shown in
Operation as a Clock Slave with Auto-Detect
LRCK and SCLK operate as inputs in clock Slave Mode. It is recommended that the left/right clock be
synchronously derived from the master clock and must be equal to Fs. It is also recommended that the
serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system
performance.
A unique feature of the CS5341 is the automatic selection of either Single-, Double- or Quad-Speed Mode
when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode
pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio
sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are
not supported when operating with a fast MCLK (512x, 256x, 128x for Single-, Double-, and Quad-Speed
Modes, respectively). Please refer to
Figure
18.
÷ 1
÷ 2
Auto-Select
Figure 18. CS5341 Master Mode Clocking
1
0
Table 1
for supported sample rate ranges.
÷ 256
÷ 128
÷ 64
÷ 4
÷ 2
÷ 1
Double
Double
Speed
Speed
Speed
Single
Speed
Speed
Speed
Single
Quad
Quad
M1
00
01
10
00
01
10
M0
LRCK Output
SCLK Output
(Equal to Fs)
CS5341
DS564F1