CS5364-DQZ Cirrus Logic Inc, CS5364-DQZ Datasheet - Page 23

• Manufacturer Part Number: CS5364-DQZ
• Description: IC,A/D CONVERTER,QUAD,24-BIT,QFP,48PIN
• Manufacturer: Cirrus Logic Inc

Specifications of CS5364-DQZ

• Number Of Bits: 24
• Sampling Rate (per Second): 216k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 580mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CDB5364 - EVALUATION BOARD FOR CS5364
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1697

DS625F4
4.5.2 TDM Format
4.5.3 Configuring Serial Audio Interface Format
4.6
4.6.1 Sample Rate Ranges
4.6.2 Using M1 and M0 to Set Sampling Parameters
TDM OUT
SCLK
FS
Speed Modes
In TDM Mode, all four channels of audio data are serially clocked out during a single Frame Sync (FS) cy-
cle, as shown in
nel slot occupies 32 SCLK cycles, with the data left justified and with MSB first. TDM output data should be
latched on the rising edge of SCLK within time specified under
on page
TDM data. All SDOUT pins will remain active during TDM Mode. Refer to
mance in TDM Mode” on page 29
The serial audio interface format of the data is controlled by the configuration of the DIF1 and DIF0 pins in
Stand-Alone Mode or by the DIF[1] and DIF[0] bits in the Global Mode Control Register in Control Port
Mode, as shown in
CS5364 supports sampling rates from 2 kHz to 21 kHz, divided into three ranges: 2 kHz - 54 kHz, 54 kHz -
108 kHz, and 108 kHz - 216 kHz. These sampling speed modes are called Single-Speed Mode (SSM),
Double-Speed Mode (DSM), and Quad-Speed Mode (QSM), respectively.
The Master/Slave operation and the sample rate range are controlled through the settings of the M1 and
M0 pins in Stand-Alone Mode, or by the M[1] and M[0] bits in the Global Mode Control Register in Control
Port Mode, as shown in
MSB
LSB
M1
0
0
1
1
MSB
Data
16. The TDM data output port resides on the SDOUT1 pin. The TDM output pin is complimentary
Channel 1
32 clks
LSB
M0
0
1
0
1
LSB
Zeroes
Figure
DIF1
MSB
0
0
1
1
Table
Channel 2
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12. The rising edge of FS signifies the start of a new TDM frame cycle. Each chan-
Table
DIF0
2.
LSB
Quadruple-Speed Master Mode (QSM)
0
1
0
1
Double-Speed Master Mode (DSM)
Single-Speed Master Mode (SSM)
Auto-Detected Speed Slave Mode
MSB
3.
Table 2. DIF1 and DIF0 Pin Settings
Channel 3
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for critical system design information.
Table 3. M1 and M0 Settings
Figure 12. TDM Format
LSB
MSB
Mode
Channel 4
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LSB
Left-Justified
Reserved
Mode
TDM
I²S
32 clks
‘Serial Audio Interface - TDM Timing” section
32 clks
Section 4.11 “Optimizing Perfor-
Frequency Range
32 clks
108 kHz - 216 kHz
54 kHz - 108 kHz
2 kHz - 216 kHz
2 kHz - 54 kHz
32 clks
CS5364
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