CS5364-DQZ Cirrus Logic Inc, CS5364-DQZ Datasheet - Page 24

• Manufacturer Part Number: CS5364-DQZ
• Description: IC,A/D CONVERTER,QUAD,24-BIT,QFP,48PIN
• Manufacturer: Cirrus Logic Inc

Specifications of CS5364-DQZ

• Number Of Bits: 24
• Sampling Rate (per Second): 216k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 580mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CDB5364 - EVALUATION BOARD FOR CS5364
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1697

24
4.6.3 Master Mode Clock Dividers
4.6.4 Slave Mode Audio Clocking With Auto-Detect
MCLK
External
MCLK
pin
bit
Figure 13
cluding the significance of each MCLK divider pin (in Stand-Alone Mode) or bit (in Control Port Mode).
In Slave Mode, CS5364 auto-detects speed mode, which eliminates the need to configure M1 and M0 when
changing among speed modes. The external MCLK is subject to clock dividers as set by the clock divider
pins in Stand-Alone Mode or the clock divider bits in Control Port Mode. The CS5364 compares the divided-
down, internal MCLK to the incoming LRCK/FS and sets the speed mode based on the MCLK/LRCK ratio
as shown in
pin
bit
CLKMODE
CLKMODE
CLKMODE
CLKMODE
÷ 1.5
0/1
÷ 1
MCLK DIVIDERS
÷ 1.5
shows the configuration of the MCLK dividers and the sample rate dividers for Master Mode, in-
0/1
÷ 1
Figure
MCLK DIVIDERS
MDIV1
MDIV
0/1
÷ 1
÷ 2
MDIV1
MDIV
14.
0/1
÷ 1
÷ 2
MDIV0
0/1
n/a
Figure 14. Slave Mode Auto-Detect Speed
÷ 1
÷ 2
MDIV0
Figure 13. Master Mode Clock Dividers
0/1
n/a
÷ 1
÷ 2
Internal
MCLK
÷LRCK
LRCK
SAMPLE RATE DIVIDERS
÷ 256
÷ 128
÷ 64
÷ 4
÷ 2
÷ 1
Double
Single
Speed
Speed
Speed
Double
Single
Speed
Speed
Speed
Quad
Quad
256
128
M1
64
00
01
10
SPEED MODE
00
01
10
M0
Double-Speed
Single-Speed
Quad-Speed
CS5364
SCLK
DS625F4
LRCK/ FS