CS5376A-IQZR Cirrus Logic Inc, CS5376A-IQZR Datasheet - Page 5

• Manufacturer Part Number: CS5376A-IQZR
• Description: IC LP Multi-Channel Decimation Filter
• Manufacturer: Cirrus Logic Inc

Specifications of CS5376A-IQZR

• Filter Type: Digital
• Number Of Filters: 4
• Max-order: 2nd
• Voltage - Supply: 3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1778 - EVALUATION BOARD FOR CS5376
• Frequency - Cutoff Or Center: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CS5376A
Figure 14. EEPROM Configuration Block Diagram . . . . . . . . . . . . . . . . . . . . . .26
Figure 15. SPI 1 EEPROM Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 16. 8 Kbyte EEPROM Memory Organization. . . . . . . . . . . . . . . . . . . . . .28
Figure 17. Serial Peripheral Interface 1 (SPI 1) Block Diagram . . . . . . . . . . . . .32
Figure 18. Microcontroller Serial Transactions . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 19. SPI 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 20. Modulator Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 21. Digital Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 22. FIR and IIR Coefficient Set Selection Word. . . . . . . . . . . . . . . . . . . .42
Figure 23. SINC Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 24. SINC Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 25. FIR Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 26. FIR Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Figure 27. Minimum Phase Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Figure 28. IIR Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 29. IIR Filter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 30. Gain and Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Figure 31. Serial Data Port Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Figure 32. SD Port Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Figure 33. SD Port Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Figure 34. Test Bit Stream Generator Block Diagram . . . . . . . . . . . . . . . . . . . .64
Figure 35. Time Break Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 36. GPIO Bi-directional Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 37. Serial Peripheral Interface 2 (SPI 2) Block Diagram . . . . . . . . . . . . .70
Figure 38. SPI 2 Master Mode Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Figure 39. SPI 2 Transaction Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Figure 40. JTAG Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Figure 41. SPI 1 Control Register SPI1CTRL. . . . . . . . . . . . . . . . . . . . . . . . . . .82
Figure 42. SPI 1 Command Register SPI1CMD . . . . . . . . . . . . . . . . . . . . . . . . .83
Figure 43. SPI 1 Data Register SPI1DAT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Figure 44. SPI 1 Data Register SPI1DAT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Figure 45. Hardware Configuration Register CONFIG . . . . . . . . . . . . . . . . . . . .87
Figure 46. GPIO Configuration Register GPCFG0 . . . . . . . . . . . . . . . . . . . . . . .88
Figure 47. GPIO Configuration Register GPCFG1 . . . . . . . . . . . . . . . . . . . . . . .89
Figure 48. SPI 2 Control Register SPI2CTRL. . . . . . . . . . . . . . . . . . . . . . . . . . .90
Figure 49. SPI 2 Command Register SPI2CMD . . . . . . . . . . . . . . . . . . . . . . . . .91
Figure 50. SPI 2 Data Register SPI2DAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Figure 51. Filter Configuration Register FILTCFG . . . . . . . . . . . . . . . . . . . . . . .93
Figure 52. Gain Correction Register GAIN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Figure 53. Offset Correction Register OFFSET1 . . . . . . . . . . . . . . . . . . . . . . . .95
Figure 54. Time Break Counter Register TIMEBRK . . . . . . . . . . . . . . . . . . . . . .96
Figure 55. Test Bit Stream Configuration Register TBSCFG . . . . . . . . . . . . . . .97
Figure 56. Test Bit Stream Gain Register TBSGAIN . . . . . . . . . . . . . . . . . . . . .98
Figure 57. User Defined System Register SYSTEM1. . . . . . . . . . . . . . . . . . . . .99
Figure 58. Hardware Version ID Register VERSION . . . . . . . . . . . . . . . . . . . .100
Figure 59. Self Test Result Register SELFTEST . . . . . . . . . . . . . . . . . . . . . . .101
DS612F4
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