CS5510-ASZR Cirrus Logic Inc, CS5510-ASZR Datasheet
CS5510-ASZR
Specifications of CS5510-ASZR
Related parts for CS5510-ASZR
CS5510-ASZR Summary of contents
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... To accommodate these applications, the ADCs include a fourth-order ΔΣ modulator and a digital filter. When configured with an external master clock of 32.768 kHz, the filter in the CS5510/12 provides better than simultaneous 50 and 60 Hz line rejection, and outputs conversion words at 53.5 Sps. The CS5511/13 include an on-chip oscillator which eliminates the need for an ex- ternal clock source ...
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... Voltage Reference Input .................................................................................................. 10 2.2.1 Voltage Reference Input Model ........................................................................... 11 2.3 Power Supply Arrangements ........................................................................................... 11 2.3.1 Digital Logic Levels ............................................................................................. 11 2.4 Clock Generator ............................................................................................................... 14 2.4.1 External Clock Source for CS5510/12 ................................................................ 14 2.4.2 Internal Oscillator for CS5511/13 ........................................................................ 14 2.5 Performing Conversions .................................................................................................. 15 2.5.1 Reading Conversions - CS5510/12 ..................................................................... 16 2.5.2 Reading Conversions - CS5511/13 ..................................................................... 16 2 ...
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... Figure 19. Data Word Timing for the CS5513............................................................................... 17 Figure 20. Digital Filter Response................................................................................................. 19 LIST OF TABLES Table 1. CS5512/13 Output Conversion Data Register Description (Flags + 20 bits). ................. 18 Table 2. CS5510/11 Output Conversion Data Register Description (Flags + 16 bits). ................. 18 Table 3. CS5510/11/12/13 Output Coding. ................................................................................... 18 Table 4. Digital Filter Response at 32.768 kHz............................................................................ 19 DS337F4 ...
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... CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (T = 25° ±5 VREF = 2.5 V (relative to V-); A CS5510/12, SCLK = 32.768 kHz; CS5511/13, f CS5510/12; OWR = 107 Sps ± 50% for CS5511/13) (See Note 1.) Parameter Accuracy Linearity Error (CS5510/11) Linearity Error (CS5512/13) No Missing Codes (CS5510/11) No Missing Codes (CS5512/13) Bipolar Offset (CS5510/11) ...
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... I may not always be the same value Symbol V CS and SCLK (Note 13 SCLK (Note 14 SDO 5.0mA V source (Note 14) SDO 1.0mA V sink SCLK SCLK I Low CS5510/11/12/13 Min Typ Max 2.5 (V 4.75 5 5.25 - 275 360 - 290 380 - 360 470 - 385 500 - ...
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... CS5510/12 OWR CS5511/13 OWR t s Symbol (Note 16) Positive V+ Negative V- (Notes 17 and 18 OUT (Note 19) PDN AIN pins V (V-)+(-0.3) INA V ( IND stg CS5510/11/12/13 Ratio Units SCLK osc SCLK/612 Sps f /612 Sps osc 4/OWR s Min Typ Max Unit -0.3 - +6.0 V -6 ±10 ...
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... On the CS5510/12, the serial clock input (SCLK) provides the master clock to operate the converter as well as the serial data clock used to read conversion data. If SCLK is held high (logic 1) for t the CS5510/12 enters sleep. To exit from sleep mode, SCLK must be held low (logic 0) for t longer. ...
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... Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 8 (Note 23) (Note 24) SCLK (Notes 24 and 25) (Notes 24 and 25) t (Note 26) CSB SCLK SDO (Note 26) CSB SCLK SDO Pulse Width High Pulse Width Low time. SLP or longer. WAKE CS5510/11/12/ pF) L Symbol Min Typ Max 100 osc - - -0. ...
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... t11 Figure 1. SDO Read Timing CS5510/12 (Not to Scale t11 Figure 2. SDO Read Timing CS5511/13 (Not to Scale). DS337F4 CS5510/11/12/ t10 ...
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... To accommodate these applications, the ADCs in- clude a fourth-order ΔΣ modulator and a digital fil- ter. When configured with an external master clock of 32.768 kHz, the filter in the CS5510/12 provides better than simultaneous 50 and 60 Hz line rejection, and outputs conversion words at 53.5 Sps. The CS5511/13 include an on-chip oscil- lator which eliminates the need for an external clock source ...
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... ADCs be balanced, however, they must sum to five volts. Figure 8 illustrates the ADCs configured with V+ = +3.3 V and V- = -1.7 V, accommodating a +3.3 V digital supply. 2.3.1 The many power supply configurations available in the CS5510/11/12/13 allow for a wide range of dig- ital logic levels. The logic-high input and output lev- 3.5 4 4.5 5 els are determined by the V+ pin ...
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... V Supply Differential Input (± 80% VREF) Common Mode = Figure 6. CS5510/11/12/13 Configured with a +5.0 V Analog Supply. +2.5 V Supply Differential Input (± 80% VREF) Common Mode = -2.5 V Supply Figure 7. CS5510/11/12/13 Configured with ±2.5 V Analog Supplies. 12 0.1 μ VREF Voltage + CS5510/11/12/13 Reference - 2 AIN AIN 0.1 μ F ...
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... V/+3.0V Supply Differential Input (± 80% VREF) Common Mode = -1.7 V/-2.0V Supply Figure 8. CS5510/11/12/13 Configured with V+ = +3.3 V and +3.0 V and V- = -2.0 V. DS337F4 0.1 μ VREF Voltage + CS5510/11/12/13 Reference - 2 AIN+ + SDO - 3 AIN- SCLK + - V- 7 0.1 μ F CS5510/11/12/ 3.3 V/3. Serial Data ...
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... Such a microcontroller circuit is shown in Figure 13. Note that the CS5510 can operate with an exter- nal, CMOS-compatible clock at frequencies up to 130 kHz, and the CS5512 can operate with an ex- ternal clock 200 kHz with a maximum jitter. Linearity performance is degraded slightly with higher clock speeds, as shown in Figures 14 and 15 ...
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... Keep in mind that in the CS5510/12, SCLK provides the external clock source for the converter. Data is clocked from the CS5510/12 at the rate set by the external clock source (typically 32.768 kHz). The CS5511/13 pro- vides an on-chip oscillator for the master clock. In ...
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... Note that if CS goes to a logic-high state during a read, the current conversion data will be lost and replaced Figure 16. Data Word Timing for the CS5510 new conversion word when the new conver- sion data is available. 2.5.2 Reading Conversions - ...
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... Output Coding As shown in Tables 1 and 2, the CS5510/11/12/13 present output conversions as 24-bit conversion words. The first bit of the conversion word indi- cates that a conversion is done through SDO fall- ing from a logic high to a logic low level. The first and the fourth bits output will always be zero. The second and third bits are error flags, representing an overflow or oscillation condition ...
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... D22 D21 D20 D11 D10 Table 2. CS5510/11 Output Conversion Data Register Description (Flags + 16 bits). 18 Two's Complement (20-Bit) 7FFFF 7FFFF ----- 7FFFE 00000 ----- FFFFF 80001 ----- 80000 Table 3. CS5510/11/12/13 Output Coding. (CLK represents SCLK for the CS5510/12 and the internal oscillator for the CS5511/13). The filters are optimized to yield better than 80 dB rejection between ...
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... If maximum throughput is required in a multiplexed application, the multiplexer must be switched at the correct time during the data collection process. For maximum throughput with the CS5510/12, switch- ing of a multiplexer should occur 595 SCLK cycles after SDO falls. For maximum throughput with the ...
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... In the 20-bit devices (CS5512 and CS5513), multiple conversions can be averaged to arrive at a more accurate offset val- ue. In the 16-bit devices (CS5510 and CS5511), averaging may not be meaningful, because the noise will be below the size of one LSB when using nominal voltages for VREF (2 ...
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... Schmitt trigger to allow for slow rise and fall time signals. If held high, the device will enter sleep mode. In the CS5510/12, this input is also used as a master clock source which determines conversion speeds and throughput. In the CS5511/13, SCLK is only used to read the conversion data and put the part in sleep mode ...
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... The deviation of the last code transition from the ideal [{(VREF) - (V-)} - 3/2 LSB]. Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). Units are in LSBs.LK 22 CS5510/11/12/13 DS337F4 ...
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... CS5511-ASZ CS5512-BSZ CS5513-BSZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS337F4 Resolution Linearity Error (Max) Temperature Range ±0.003% 16 Bits ±0.0015% 20 Bits Peak Reflow Temp MSL Rating* 260 °C CS5510/11/12/13 Package 8-pin SOIC -40°C to +85°C Lead-free Max Floor Life 3 7 Days 23 ...
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... EIAJ PACKAGE Controlling Dimension is Inches CS5510/11/12/13 ∝ L MILLIMETERS MIN NOM MAX 1.93 2.03 2.13 0.10 0.175 0.25 0.33 0.406 0.51 0.15 0.20 0.25 5.23 5 ...
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... REVISION HISTORY Revision Date F2 MAR 2005 Added lead-free (Pb) device ordering information. F3 AUG 2005 Updated lead-free (Pb) device ordering information. Added MSL data. F4 JUL 2009 Removed devices containing lead (Pb) from ordering information. DS337F4 CS5510/11/12/13 Changes 25 ...
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... ING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. 26 www.cirrus.com CS5510/11/12/13 DS337F4 ...