CS61584A-IQ3Z Cirrus Logic Inc, CS61584A-IQ3Z Datasheet - Page 25

• Manufacturer Part Number: CS61584A-IQ3Z
• Description: IC,Line Interface,QFP,64PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61584A-IQ3Z

• Interface: Parallel/Serial
• Voltage - Supply: 3.3V, 5V
• Package / Case: 64-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1713

Latched-AIS: Set high on the rising edge of the
alarm indication signal condition. Reading the Sta-
tus register clears the Latched-AIS bit and deacti-
vates the INT pin. Refer to the timing diagram in
Figure 18.
Latched-BPV: Indicates a bipolar violation has
been received since the last read of the Status reg-
ister. Reading the Status register clears the
Latched-BPV bit and deactivates the INT pin. This
bit is set only when the line code decoder is enabled
in the Control A register.
Latched-Overflow: Indicates a waveform generat-
ed using the Arbitrary Waveform register has ex-
ceeded full scale since the last read of the Status
register. Reading the Status register clears the
Latched-Overflow bit and deactivates the INT pin.
Latched-Reset: Indicates a reset event (power-up or
RESET pin) has occurred since the last read of the
DS261PP5
DS261F1
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Mask LOS1
Mask Latched-LOS1
Mask AIS1
Mask Latched-AIS1
Mask Latched-BPV1
Mask Latched-Overflow1
Automatic All Ones, AAO
Mask Interrupt1
Mask LOS2
Mask Latched-LOS2
Mask AIS2
Mask Latched-AIS2
Mask Latched-BPV2
Mask Latched-Overflow2
Mask Latched-CLKLOST
Mask Interrupt2
Description
Description
Serial Port Address: 0x12; Parallel Port Address: 0xY2
Serial Port Address: 0x13; Parallel Port Address: 0xY3
Mask Interrupt
Mask Interrupt
Mask Interrupt
Mask Interrupt
Mask Interrupt
Mask Interrupt
Ones at RPOS/NEG on LOS
Mask Interrupt
Mask Interrupt
Mask Interrupt
Mask Interrupt
Mask Interrupt
Mask Interrupt
Mask Interrupt
Mask Interrupt
Mask Interrupt
Mask Register (Channel 1)
Mask Register (Channel 2)
Table 6. Mask Registers
DS261PP5
1
1
Status register. Reading the Status register clears
the Latched-Reset bit and deactivates the INT pin.
This bit is not maskable.
Latched-CLKLOST: Set high when TCLK or REF-
CLK are absent. Reading the Status register clears
the Latched-CLKLOST bit and deactivates the INT
pin.
Interrupt: Indicates a change in the Status register
since the last read. Reading the Status register
clears the Interrupt bit and deactivates the INT pin.
9.1.2
The Mask registers are read-write registers and are
shown in Table 6. The Mask registers disables the
interrupts in the corresponding Status register on a
per-bit basis. Masking a Status register bit forces it
to remain at zero and prevents the INT pin from ac-
tivating on the condition.
Definition
Definition
Mask Registers
Enable Interrupt
Enable Interrupt
Enable Interrupt
Enable Interrupt
Enable Interrupt
Enable Interrupt
Zeros at RPOS/NEG on LOS
Enable Interrupt
Enable Interrupt
Enable Interrupt
Enable Interrupt
Enable Interrupt
Enable Interrupt
Enable Interrupt
Enable Interrupt
Enable Interrupt
0
0
CS61584A
CS61584A
Reset
Reset
Value
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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