CS61584A-IQ3Z Cirrus Logic Inc, CS61584A-IQ3Z Datasheet - Page 45
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CS61584A-IQ3Z
Manufacturer Part Number
CS61584A-IQ3Z
Description
IC,Line Interface,QFP,64PIN,PLASTIC
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS61584A-IQ3Z.pdf
(54 pages)
Specifications of CS61584A-IQ3Z
Interface
Parallel/Serial
Voltage - Supply
3.3V, 5V
Package / Case
64-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
598-1713
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS61584A-IQ3Z
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS61584A-IQ3Z
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
CS61584A-IQ3ZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Status
AIS1, AIS2 - Alarm Indication Signal [Host mode] (PLCC pins 15, 54; TQFP pins 6, 43)
BPV1, BPV2 - Bipolar Violation [Host mode] (PLCC pins 12, 57; TQFP pins 3, 46)
LOS1 - Loss of Signal [Hardware mode and Host mode - serial port]
LOS2 - (PLCC pins 16, 53; TQFP pins 7, 42)
Test
J-TCK - JTAG Test Clock (PLCC pin 51; TQFP pin 40)
J-TMS - JTAG Test Mode Select (PLCC pin 50; TQFP pin 39)
J-TDI - JTAG Test Data In (PLCC pin 19; TQFP pin 10)
J-TDO - JTAG Test Data Out (PLCC pin 17; TQFP pin 8)
DS261PP5
DS261F1
The AIS indication goes high when the receiver detects 99.9% ones density in a 5.3 ms period (< 9
zeros in 8192 bits). The AIS indication returns low when the receiver detects
The BPV indication goes high for one RCLK bit period when a bipolar violation is detected in the
received signal. Bipolar violations caused by B8ZS (or HDB3) zero substitutions are not flagged by the
BPV pin if the coder mode is enabled.
The BPV pin also goes high for one RCLK bit period on excessive zero events if EXZ = 1 (Control A
register, channel 2). In AMI mode, the BPV pin goes high when 16 or more zeros are received. In B8ZS
mode, the BPV pin goes high when 8 or more zeros are received. This functionality is disabled when
the device is configured for E1 operation.
The LOS indication goes high when 175 ±15 consecutive zeros are received on the line interface, or
when the receive (RTIP/RRING) signal level drop below the receiver sensitivity of the device. The LOS
indication returns low when a minimum 12.5% ones density signal over 175 ±75 bit periods with no
more than 100 consecutive zeros is received.
Data on pins J-TDI and J-TDO is valid on the rising edge of J-TCK. When J-TCK is stopped low, all
JTAG registers remain unchanged.
An active high signal on J-TMS enables the JTAG serial port. This pin has an internal pull-up resistor
and may be unconnected to float high or tied low while the JTAG interface is not active.
JTAG data is shifted into the device on this pin. This pin has an internal pull-up resistor. Data must be
stable on the rising edge of J-TCK.
JTAG data is shifted out of the device on this pin. This pin is active only when JTAG testing is in
progress. J-TDO will be updated on the falling edge of J-TCK.
DS261PP5
9 zeros in 8192 bits.
CS61584A
CS61584A
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