CS8415A-CZ Cirrus Logic Inc, CS8415A-CZ Datasheet - Page 14

• Manufacturer Part Number: CS8415A-CZ
• Description: Receiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8415A-CZ

• Driver Case Style: TSSOP
• No. Of Pins: 28
• Mounting Type: Surface Mount
• No. Of Channels: 7
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• Supply Voltage Max: 5V
• Leaded Process Compatible: No
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

one resistor required. There are two sets of compo-
nent values recommended, depending on the sam-
ple rate of the application, see Table 1. The default
set, called “fast”, accommodates input sample rates
of 32 kHz to 96 Hz with no component changes. It
has the highest corner frequency jitter attenuation
curve, and takes the shortest time to lock. The alter-
nate component set, called “medium” allows the
lowest input sample rate to be 8 kHz, and increases
the lock time of the PLL. Lock times are worst case
for an Fsi transition of 96 kHz.
5.3
While decoding the incoming AES3 data stream,
the CS8415A can identify several kinds of error,
indicated in the Receiver Error register. The UN-
LOCK bit indicates whether the PLL is locked to
the incoming AES3 data. The V bit reflects the cur-
14
-10
-15
-20
-25
-30
-35
-40
-45
-5
Figure 7. Jitter Attenuation Characteristics of PLL
5
0
10
-1
Error Reporting and Hold Function
with 8-96 kHz Fs Filter Components
10
0
10
Fs Range (kHz) RFILT (kΩ) CFILT (µF) CRIP (nF) PLL Lock Time
1
32 to 96
8 to 96
Digital Bode plot
Frequency (Hz)
10
2
Table 1. PLL External Component Values
10
3
0.909
3.0
10
4
0.047
10
1.8
5
rent validity bit status. The CONF (confidence) bit
indicates the amplitude of the eye pattern opening,
indicating a link that is close to generating errors.
The BIP (bi-phase) error bit indicates an error in in-
coming bi-phase coding. The PAR (parity) bit indi-
cates a received parity error.
The error bits are "sticky": they are set on the first
occurrence of the associated error and will remain
set until the user reads the register through the con-
trol port. This enables the register to log all un-
masked errors that occurred since the last time the
register was read.
The Receiver Error Mask register allows masking
of individual errors. The bits in this register serve
as masks for the corresponding bits of the Receiver
Error Register. If a mask bit is set to 1, the error is
unmasked, which implies the following: its occur-
-10
-15
-20
-25
-30
-35
-40
-45
-5
10
5
0
Figure 8. Jitter Attenuation Characteristics of PLL
-1
2.2
33
with 32-96 kHz Fs Filter Components
10
0
10
1
56
35
Digital Bode plot
Frequency (Hz)
10
2
10
3
CS8415A
DS470PP3
10
4
10
5