CY62146ELL-45ZSXAT Cypress Semiconductor Corp, CY62146ELL-45ZSXAT Datasheet

CY62146ELL-45ZSXAT

CY62146ELL-45ZSXAT

Manufacturer Part Number
CY62146ELL-45ZSXAT
Description
CY62146ELL-45ZSXAT
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62146ELL-45ZSXAT

Format - Memory
RAM
Memory Type
SRAM
Memory Size
4M (256K x 16)
Speed
45ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
Functional Description
The CY62146E is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life (MoBL
Cypress Semiconductor Corporation
Document Number: 001-07970 Rev. *G
Logic Block Diagram
Very high speed: 45 ns
Wide voltage range: 4.5 V to 5.5 V
Ultra low standby power
Ultra low active power
Easy memory expansion with CE and OE features
Automatic power down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Available in Pb-free 44-pin thin small outline package (TSOP)
II package
Typical standby current: 1 A
Maximum standby current: 7 A
Typical active current: 2 mA at f = 1 MHz
A
A
A
A
A
A
A
A
A
A
A
3
2
1
0
9
8
7
6
5
4
10
198 Champion Court
COLUMN DECODER
DATA IN DRIVERS
) in portable
RAM Array
256K x 16
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
when addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99% when
deselected (CE HIGH). The input and output pins (I/O
I/O
deselected (CE HIGH), the outputs are disabled (OE HIGH),
both Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH) or during a write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O
specified on the address pins (A
Enable (BHE) is LOW, then data from I/O pins (I/O
I/O
(A
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O
of read and write modes.
For best practice recommendations, refer to the Cypress
application note
4-Mbit (256K x 16) Static RAM
0
15
15
through A
) are placed in a high impedance state when the device is
) is written into the location specified on the address pins
San Jose
17
8
).
AN1064, SRAM System
to I/O
0
through I/O
,
15
CA 95134-1709
I/O
I/O
. See
0
8
–I/O
–I/O
BHE
WE
CE
OE
BLE
Table
7
15
CY62146E MoBL
7
) is written into the location
0
through A
for a complete description
Revised January 20, 2011
Guidelines.
17
). If Byte High
408-943-2600
0
8
0
to I/O
through
through
7
. If
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CY62146ELL-45ZSXAT Summary of contents

Page 1

... Cypress Semiconductor Corporation Document Number: 001-07970 Rev. *G 4-Mbit (256K x 16) Static RAM applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH) ...

Page 2

Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 4 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... ...

Page 3

... Pin Configuration Product Portfolio Product Range Min CY62146ELL Ind’l/Auto-A 4.5 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V Document Number: 001-07970 Rev. *G Figure 1. 44-Pin TSOP II (Top View) ...

Page 4

... Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I 8. Tested initially after any design or process changes that may affect these parameters. Document Number: 001-07970 Rev. *G Output current into outputs (LOW) .............................. 20 mA Static discharge voltage............................................ >2001 V (MIL-STD-883, Method 3015) Latch-up current ...................................................... >200 mA Operating Range Device CY62146ELL Test Conditions I = –1 2 4.5 < V < ...

Page 5

OUTPUT 30 pF INCLUDING JIG AND SCOPE Parameters Data Retention Characteristics Over the Operating Range Parameter Description V V for data retention DR CC [10] I Data retention current CCDR t ...

Page 6

Switching Characteristics Over the Operating Range Parameter [13, 14] Read Cycle t Read cycle time RC t Address to data valid AA t Data hold from address change OHA t CE LOW to data valid ACE t OE LOW to ...

Page 7

Switching Waveforms Figure 4. Read Cycle No.1: Address Transition Controlled ADDRESS DATA OUT PREVIOUS DATA VALID Figure 5. Read Cycle No Controlled ADDRESS CE t ACE OE t LZOE BHE/BLE t LZBE HIGH IMPEDANCE DATA OUT t LZCE ...

Page 8

Switching Waveforms (continued) Figure 6. Write Cycle Controlled ADDRESS BHE/BLE OE NOTE 24 DATA I/O t HZOE ADDRESS CE WE BHE/BLE OE DATA I/O NOTE 24 t HZOE Notes 21 HIGH ...

Page 9

Switching Waveforms (continued) Figure 8. Write Cycle 3: WE controlled, OE LOW ADDRESS CE BHE/BLE DATA I/O NOTE 26 Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW ADDRESS CE BHE/BLE NOTE 26 DATA ...

Page 10

Truth Table BHE BLE [27 [27 ...

Page 11

... Ordering Information Speed Ordering Code (ns) 45 CY62146ELL-45ZSXI CY62146ELL-45ZSXA Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions E LL 621 ZSX CY 6 Package Diagram 22 23 TOP VIEW 0.400(0.016) 0.800 BSC 0.300 (0.012) (0.0315) 18.517 (0.729) 18.313 (0.721) DIMENSION IN MM (INCH) MAX MIN ...

Page 12

Acronyms Acronym Description CMOS complementary metal oxide semiconductor I/O input/output SRAM static random access memory TSOP thin small outline package Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V volts µA micro amperes mA milli amperes ...

Page 13

Document History Page  Document Title: CY62146E MoBL 4-Mbit (256K x 16) Static RAM Document Number: 001-07970 REV. ECN NO. Issue Date ** 463213 See ECN *A 684343 See ECN *B 925501 See ECN *C 1045260 See ECN *D 2073548 ...

Page 14

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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