CY7B923-SXCT Cypress Semiconductor Corp, CY7B923-SXCT Datasheet - Page 10

• Manufacturer Part Number: CY7B923-SXCT
• Description: CY7B923-SXCT
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink™r
• Type: Transmitter and Receiverr

Specifications of CY7B923-SXCT

• Protocol: Fibre Channel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Compliant

Decoder
Parallel data is transformed from ANSI-specified X3.230 8B/10B
codes back to ‘raw data’ in the decoder. This block uses the
standard decoder patterns shown in
(SC/D = LOW) on page 21
and Sequences (SC/D = HIGH)[1, 2] on page
are signaled by a LOW on the SC/D output and special character
patterns are signaled by a HIGH on the SC/D output. Unused
patterns or disparity errors are signaled as errors by a HIGH on
the RVS output and by specific special character codes.
Output Register
The output register holds the recovered data (Q
RVS) and aligns it with the recovered byte clock (CKR). This
synchronization insures proper timing to match a FIFO interface
or other logic that requires glitch-free and specified output
behavior. Outputs change synchronously with the rising edge of
CKR.
In BIST mode, this register becomes the signature pattern
generator and checker by logically converting itself into a linear
feedback shift register (LFSR) pattern generator. When enabled,
this LFSR generates a 511-byte sequence that includes all data
and special character codes, including the explicit violation
symbols. This pattern provides a predictable but pseudo-random
sequence that can be matched to an identical LFSR in the Trans-
mitter. When synchronized, it checks each byte in the Decoder
with each byte generated by the LFSR and shows errors at RVS.
Patterns generated by the LFSR are compared after being
buffered to the output pins and then fed back to the comparators,
allowing test of the entire receive function.
In BIST mode, the LFSR is initialized by the first occurrence of
the transmitter BIST loop start code D0.0 (D0.0 is sent only once
per BIST loop). Once the BIST loop has been started, RVS will
be HIGH for pattern mismatches between the received sequence
and the internally generated sequence. Code rule violations or
running disparity errors that occur as part of the BIST loop will
not cause an error indication. RDY will pulse HIGH once per
BIST loop and can be used to check test pattern progress. The
receiver BIST generator can be reinitialized by leaving and
re-entering BIST mode.
Test Logic
Test logic includes the initialization and control for the Built-In
Self-Test (BIST) generator, the multiplexer for Test mode clock
distribution, and control logic for the decoder. Test logic is
discussed in more detail in the
Operating Mode
Document #: 38-02017 Rev. *H
Description.
and
CY7B933 HOTLink Receiver
Valid Special Character Codes
Valid Data Characters
29. Data patterns
0–7
, SC/D, and
HOTLink CY7B923 Transmitter and CY7B933
Receiver Operation
The CY7B923 Transmitter operating with the CY7B933 Receiver
form a general purpose data communications subsystem
capable of transporting user data at up to 33 Mbytes per second
(40 Mbytes per second for –400 devices) over several types of
serial interface media.
of data through the HOTLink CY7B923 transmitter pipeline. Data
is latched into the transmitter on the rising edge of CKW when
enabled by ENA or ENN. RP is asserted LOW with a 60%
LOW/40% HIGH duty cycle when ENA is LOW. RP may be used
as a read strobe for accessing data stored in a FIFO. The parallel
data flows through the encoder and is then shifted out of the
OUTx± PECL drivers. The bit-rate clock is generated internally
from a multiply-by-ten PLL clock generator. The latency through
the transmitter is approximately 21t
range. A more complete description is found in the section
CY7B923 HOTLink Transmitter Operating Mode
Figure 5
receiver pipeline. Serial data is sampled by the receiver on the
INx± inputs. The receiver PLL locks onto the serial bit stream and
generates an internal bit rate clock. The bit stream is deseri-
alized, decoded and then presented at the parallel output pins.
A byte rate clock (bit clock  10) synchronous with the parallel
data is presented at the CKR pin. The RDY pin will be asserted
to LOW to indicate that data or control characters are present on
the outputs. RDY will not be asserted LOW in a field of K28.5s
except for any single K28.5 or the last one in a continuous series
of K28.5’s. The latency through the receiver is approximately
24t
description of the receiver is in the section
Receiver Operating Mode
The HOTLink receiver has a built-in byte framer that synchro-
nizes the Receiver pipeline with incoming SYNC (K28.5)
characters.
framing operation. The Framer is enabled when the RF pin is
asserted HIGH. RF is latched into the receiver on the falling edge
of CKR. The framer looks for K28.5 characters embedded in the
serial data stream. When a K28.5 is found, the framer sets the
parallel byte boundary for subsequent data to the K28.5
boundary. While the framer is enabled, the RDY pin indicates the
status of the framing operation.
When the RF pin is asserted HIGH, RDY leaves it normal mode
of operation and is asserted HIGH while the framer searches the
data stream for a K28.5 character. After the framer has synchro-
nized to a K28.5 character, the Receiver will assert the RDY pin
LOW when the K28.5 character is present at the parallel output.
The RDY pin will then resume its normal operation as dictated by
the MODE and BISTEN pins.
The normal operation of the RDY pin in encoded mode is to
signal when parallel data is present at the output pins by pulsing
LOW with a 60% LOW/40% HIGH duty cycle. RDY does not
pulse LOW in a field of K28.5 characters; however, RDY does
pulse LOW for the last K28.5 character in the field or for any
single K28.5. In unencoded mode, the normal operation of the
RDY pin is to signal when any K28.5 is at the parallel output pins.
B
+ 10 ns over the operating range. A more complete
illustrates the data flow through the HOTLink CY7B933
Figure
illustrates the HOTLink CY7B933 Receiver
Figure 10 on page 33
Description.
CY7B923, CY7B933
B
– 10 ns over the operating
CY7B933 HOTLink
illustrates the flow
Description.
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