CY7B994V-2AXIT Cypress Semiconductor Corp, CY7B994V-2AXIT Datasheet - Page 6

• Manufacturer Part Number: CY7B994V-2AXIT
• Description: IC,Eighteen Distributed-Output Clock Driver,QFP,100PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp
• Series: RoboClock™r
• Type: Clock Buffer, Fanout Distributionr

Specifications of CY7B994V-2AXIT

• Pll: Yes
• Input: LVPECL, LVTTL
• Output: LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 4:18
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. Pin Definition (continued)
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept signals from the REF inputs (REFA+,
REFA–, REFB+, or REFB–) and the FB inputs (FBKA+, FBKA–,
FBKB+, or FBKB–). Correction information is then generated to
control the frequency of the voltage-controlled oscillator (VCO).
These two blocks, along with the VCO, form a PLL that tracks
the incoming REF signal.
The CY7B993V/994V have a flexible REF and FB input scheme.
These inputs allow the use of either differential LVPECL or
single-ended LVTTL inputs. To configure as single-ended LVTTL
inputs, the complementary pin must be left open (internally pulled
to 1.5V). The other input pin can then be used as an LVTTL input.
The REF inputs are also tolerant to hot insertion.
Document #: 38-07127 Rev. *I
FBDS[0:1]
FBDIS
[1:4]F[0:1]
[1:4]DS[0:1]
DIS[1:4]
INV3
LOCK
OUTPUT_MODE Input
QFA[0:1]
[1:4]Q[A:B][0:1]
VCCN
VCCQ
GND
Pin Name
Input
Input
Input
Input
Input
Input
Output LVTTL
Output LVTTL
Output LVTTL
I/O
Pin Type
3-level
Input
LVTTL
Input
3-level
Input
LVTTL
3-level
Input
3-Level
Input
PWR
PWR
PWR
3-level
[1]
Feedback Divider Function Select. These inputs determine the function of the QFA0
and QFA1 outputs (see
Feedback Disable. This input controls the state of QFA[0:1]. When HIGH, the QFA[0:1]
is disabled to the “HOLD-OFF” or “High Z” state; the disable state is determined by
OUTPUT_MODE. When LOW, the QFA[0:1] is enabled (see
internal pull-down.
Output Phase Function Select. Each pair controls the phase function of the respective
bank of outputs (see
Output Divider Function Select. Each pair controls the divider function of the respective
bank of outputs (see
Output Disable. Each input controls the state of the respective output bank. When HIGH,
the output bank is disabled to the “HOLD-OFF” or “High Z” state; the disable state is
determined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled (see
Table
Invert Mode. This input only affects Bank 3. When this input is LOW, each matched output
pair becomes complementary (3QA0+, 3QA1–, 3QB0+, 3QB1–). When this input is HIGH,
all four outputs in the same bank are inverted. When this input is MID all four outputs are
non inverting.
PLL Lock Indicator. When HIGH, this output indicates the internal PLL is locked to the
reference signal. When LOW, the PLL is attempting to acquire lock.
Output Mode. This pin determines the clock outputs’ disable state. When this input is
HIGH, the clock outputs disable to high impedance (High Z). When this input is LOW, the
clock outputs disable to “HOLD-OFF” mode. When in MID, the device enters factory test
mode.
Clock Feedback Output. This pair of clock outputs is intended to be connected to the
FB input. These outputs have numerous divide options and three choices of phase adjust-
ments. The function is determined by the setting of the FBDS[0:1] pins and FBF0.
Clock Output. These outputs provide numerous divide and phase select functions deter-
mined by the [1:4]DS[0:1] and [1:4]F[0:1] inputs.
Output Buffer Power. Power supply for each output pair.
Internal Power. Power supply for the internal circuitry.
Device Ground.
6). These inputs each have an internal pull-down.
Table
Table
Table
4).
5).
The REF inputs can be changed dynamically. When changing
from one reference input to the other of the same frequency, the
PLL is optimized to ensure that the clock output period is not less
than the calculated system budget (t
reference clock period) – t
period deviation)) while reacquiring the lock.
VCO, Control Logic, Divider, and Phase Generator
The VCO accepts analog control inputs from the PLL filter block.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (f
f
versions: a low-speed device (CY7B993V) where f
from 12 MHz to 100 MHz, and a high-speed device (CY7B994V)
that ranges from 24 MHz to 200 MHz. The FS setting for each
device is shown in
The f
CY7B994V, the upper f
200 MHz.
NOM
5).
NOM
is directly related to the VCO frequency. There are two
Pin Description
frequency is seen on “divide-by-one” outputs. For the
Table
NOM
2.
CY7B993V, CY7B994V
CCJ
(cycle-to-cycle jitter) – t
range extends from 96 MHz to
Table
6). This input has an
MIN
RoboClock
NOM
= t
) of the device.
REF
Page 6 of 18
NOM
PDEV
(nominal
ranges
(Max

[+] Feedback