CY7C0852V-133BBC Cypress Semiconductor Corp, CY7C0852V-133BBC Datasheet - Page 18

IC,SYNC SRAM,128KX36,CMOS,BGA,172PIN,PLASTIC

CY7C0852V-133BBC

Manufacturer Part Number
CY7C0852V-133BBC
Description
IC,SYNC SRAM,128KX36,CMOS,BGA,172PIN,PLASTIC
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C0852V-133BBC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
4M (128K x 36)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Package / Case
172-LFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS compliant by exemption

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C0852V-133BBC
Manufacturer:
CYPRESS
Quantity:
329
Part Number:
CY7C0852V-133BBC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C0852V-133BBCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-06059 Rev. *I
Switching Characteristics
JTAG Timing
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
Notes:
18. Except JTAG signals (t
19. This parameter is guaranteed by design, but it is not production tested.
20. Test conditions used are Load 2.
OHZ
CD2
CA2
CM2
DC
CKHZ
CKLZ
SINT
RINT
SCINT
RCINT
CCS
RS
RSS
RSR
RSF
RSCNTINT
JTAG
TCYC
TH
TL
TMSS
TMSH
TDIS
TDIH
TDOV
TDOX
Parameter
Port to Port Delays
Master Reset Timing
Parameter
[19, 20]
[19, 20]
[19, 20]
Maximum JTAG TAP Controller Frequency
TCK Clock Cycle Time
TCK Clock HIGH Time
TCK Clock LOW Time
TMS Set-up to TCK Clock Rise
TMS Hold After TCK Clock Rise
TDI Set-up to TCK Clock Rise
TDI Hold After TCK Clock Rise
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
OE to High Z
Clock to Data Valid
Clock to Counter Address Valid
Clock to Mask Register Readback Valid
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
Clock to INT Set Time
Clock to INT Reset Time
Clock to CNTINT Set Time
Clock to CNTINT Reset time
Clock to Clock Skew
Master Reset Pulse Width
Master Reset Set-up Time
Master Reset Recovery Time
Master Reset to Outputs Inactive
Master Reset to Counter Interrupt Flag Reset Time
r
and t
f
< 10 ns [max.]).
Over the Operating Range (continued)
Description
Description
Min.
1.0
1.0
0.5
0.5
0.5
0.5
5.2
7.0
6.0
6.0
0
0
-167
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Max.
4.0
4.0
4.0
4.0
4.0
4.0
6.7
6.7
5.0
5.0
6.0
5.8
CY7C0851V/CY7C0852V
Min.
100
40
40
10
10
10
10
0
Min.
-167/-133
0.5
0.5
0.5
0.5
7.5
6.0
7.5
1.0
1.0
6.0
0
0
-133
Max.
Max.
4.4
4.4
4.4
4.4
4.4
4.4
7.5
7.5
5.7
5.7
6.5
7.0
10
30
Page 18 of 32
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

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