CY7C0852V-133BBC Cypress Semiconductor Corp, CY7C0852V-133BBC Datasheet - Page 20

IC,SYNC SRAM,128KX36,CMOS,BGA,172PIN,PLASTIC

CY7C0852V-133BBC

Manufacturer Part Number
CY7C0852V-133BBC
Description
IC,SYNC SRAM,128KX36,CMOS,BGA,172PIN,PLASTIC
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C0852V-133BBC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
4M (128K x 36)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Package / Case
172-LFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS compliant by exemption

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CY7C0852V-133BBC
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Document #: 38-06059 Rev. *I
Switching Waveforms
Read Cycle
Notes:
21. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
22. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
23. The output is disabled (high-impedance state) by CE = V
24. Addresses do not have to be accessed sequentially since ADS = CNTEN = V
Numbers are for reference only.
ADDRESS
DATA
B0–B3
R/W
CLK
OUT
OE
[6, 21, 22, 23, 24]
CE
t
t
t
t
SB
SW
SA
SC
A
n
(continued)
t
t
t
t
HB
HW
HA
t
HC
CH2
1 Latency
t
CYC2
t
CKLZ
t
CL2
IH
A
n+1
following the next rising edge of the clock.
t
CD2
IL
with CNT/MSK = V
Q
A
n
n+2
IH
constantly loads the address on the rising edge of the CLK.
t
DC
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Q
t
SC
n+1
t
OHZ
A
n+3
t
OLZ
t
HC
t
OE
Page 20 of 32
Q
n+2

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