CY7C0852V-133BBCT Cypress Semiconductor Corp, CY7C0852V-133BBCT Datasheet - Page 13

CY7C0852V-133BBCT

CY7C0852V-133BBCT

Manufacturer Part Number
CY7C0852V-133BBCT
Description
CY7C0852V-133BBCT
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C0852V-133BBCT

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
4M (128K x 36)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Package / Case
172-LFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C0852V-133BBCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-06059 Rev. *I
CLAMP
The optional CLAMP instruction allows the state of the signals
driven from CY7C0851V/CY7C0852V pins to be determined
from the boundary-scan register while the BYPASS register is
selected as the serial path between TDI and TDO. CLAMP
controls boundary cells to 1 or 0.
NBSRST
This is the Non-Boundary Scan Reset instruction. NBSRST
places the Bypass Register (BYR) between TDI and TDO
when selected. Its function is to reset every logic (similar to
MRST) except that it does not reset the JTAG logic.
Notes:
13. I
14. The “0”/”1” next to each state represents the value at TMS at the rising edge of CLK.
1
0
SB3
values only if JTAG pins are not active and master reset (MRST) not enabled.
RUN_TEST/
IDLE
TEST-LOGIC
RESET
0
1
Figure 3. TAP Controller State Diagram (FSM)
1
0
SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
1
0
1
0
1
1
0
[12]
Boundary Scan Cells (BSC)
Every CY7C0851V/CY7C0852V output has two boundary
scan cells; one for data, and one for three-state control. JTAG
TAP pins (TDI, TMS, TDO, TCK), MRST, and all power and
ground pins have no scan cell. Other CY7C0851V/
CY7C0852V inputs have only the data scan cell.
Active and Standby Supply Current
When the instruction in the JTAG instruction register selects
the Boundary Scan Register (BSR) and the TAP controller is
in any state except TEST-LOGIC-RESET or RUN-TEST/IDLE,
then the device supply current (I
With the JTAG logic in this state, and both ports inactive with
CMOS input levels, it is possible for the supply current to
exceed the ISB3 value given in the Electrical Characteristics
section of this data sheet.
0
0
1
0
1
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
[14]
1
0
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
SELECT
IR-SCAN
1
CC
or I
0
0
1
1
1
0
[13]
SB1/2/3/4
0
Page 13 of 32
) will increase.
1
0
1
0

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