CY7C09569V-100AXC Cypress Semiconductor Corp, CY7C09569V-100AXC Datasheet - Page 17
![IC,SYNC SRAM,16KX36,CMOS,QFP,144PIN,PLASTIC](/photos/37/15/371545/144pin_tqfp_sml.jpg)
CY7C09569V-100AXC
Manufacturer Part Number
CY7C09569V-100AXC
Description
IC,SYNC SRAM,16KX36,CMOS,QFP,144PIN,PLASTIC
Manufacturer
Cypress Semiconductor Corp
Specifications of CY7C09569V-100AXC
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
576K (16K x 36)
Speed
100MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
Density
576Kb
Access Time (max)
12.5ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
67MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
14b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
385mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Word Size
36b
Number Of Words
16K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C09569V-100AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Bus Match Flow-Through Read-to-Write-to-Read (OE = V
Notes
Document Number: 38-06054 Rev. *E
49. Test conditions used are Load 2.
50. Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs.
51. See table “Right Port Operation“ for data output on first and subsequent cycles.
52. CNTEN = V
53. CE = ADS = CNTEN = V
54. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
55. BM, SIZE, and BE must be reconfigured 1 cycle before operation is guaranteed. BM, SIZE, and BE should remain static for any particular port configuration.
all the time except when loading the initial external address (i.e. ADS = V
Address
Data
Data
CLK
ADS
R/W
CE
OUT
IN
IL
. In x9 and x18 Bus Matching Burst Mode operations (Write or Read), ADS can toggle on the rising edge of every clock cycle or it can be at V
t
t
t
SC
SW
SA
A
n
t
t
t
t
HC
HW
HA
CH1
IL
1st Cycle
t
; CNTRST = V
CD1
t
CYC1
Read
t
CL1
1st Word
(continued)
A
Q
n
n
t
IH
DC
2nd Cycle
.
t
CD1
Read
2nd Word
A
Q
n+1
t
n
CKHZ
Operation
No
t
SW
t
1st Word
SD
A
D
n+1
IL
n+1
t
only required when reading or writing the first Byte or Word).
HW
t
HD
1st Cycle
Write
IL
2nd Word
)
[49, 50, 51, 52, 53, 54, 55]
A
D
n+1
n+1
2nd Cycle
Write
A
n+1
t
1st Cycle
CD1
t
CKLZ
Read
A
Q
n+1
n+1
2nd Cycle
t
CD1
Read
t
DC
CY7C09569V
CY7C09579V
A
Q
n+2
n+1
Page 17 of 32
IH
level
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